P型金氧半場效電晶體與薄膜輪廓工法之氧化鋅薄膜電晶體之單片整合製作與特性研究

Abstract

本篇論文研究製作單片整合P型金氧半場效電晶體與氧化鋅薄膜電晶體於6吋矽基板上，且後段氧化鋅薄膜電晶體元件的製作採用了薄膜輪廓工法來完成。在前段元件金氧半場效電晶體的部分，我們利用了常規的製程，包含了矽的局部氧化(LOCOS)、多晶矽閘極(polysilicon gate)以及自我對準(self-aligned)植入的製程來完成。在特性方面，平均元件的次臨界擺幅(subthreshold swing)大約是落在75至80 mV/decade之間，在通道長度小於1 μm的元件，也能看到有臨界電壓下降(threshold voltage roll-off)以及汲極引發位能障下降(Drain induced barrier lowering)等短通道效應。 完前段金氧半場效電晶體成後，我們使用氮化矽(Si3N4)來當作前段元件的保護層，此層氮化矽可防止後續製作後段元件所需要使用的二氧化矽蝕刻液(BOE)破壞前段元件。在氧化鋅薄膜電晶體完成之後，我們比較了在後段元件製作前後的前段元件特性，並沒有發現很顯著的劣化或改變。由於後段元件是利用薄膜輪廓工法來製作，而這一連串的實驗步驟所經歷的都是低溫製程且不具破壞與污染性，且最高溫不超過350 ℃，因此並不會影響到前段金氧半場效電晶體的特性。 在後段氧化鋅薄膜電晶體的部分，我們製作並比較兩個不同的結構，包括了上述單片整合上具有獨立金屬閘極(discrete bottom gate)，與另一種結構採用矽基板作為共閘極(common gate)，其製程僅需要一道光罩。從實驗結果可以看出，儘管獨立金屬閘極整合在前段金氧半場效電晶體上，需要較多道光罩及較複雜的製程步驟，其特性與矽基板作為閘極的元件相近但擁有更大的開關電流比(ION/IOFF)，歸因於獨立金屬閘極可有效抑制閘極漏電流。

In this thesis, we investigate the monolithic integration of the front-end-of-line (FEOL) traditional Si PMOSFETs with the back-end-of-line (BEOL) ZnO thin-film transistors (TFTs) on the same 6-inch silicon wafer. The “film profile engineering” (FPE) scheme is utilized to fabricate the sub-micron, high-performance metal-oxide TFTs. Conventional processes including LOCOS isolation, polysilicon gate, and self-aligned S/D implantation steps are implemented into the fabrication of FEOL PMOSFETs. The characteristics of the fabricated FEOL PMOSFETs are decent with SS in the range of 75~80 mV/decade, good ION/IOFF (> 107), and low gate leakage current. We also observe short-channel effects in sub-micron devices like threshold voltage roll-off and drain induced barrier lowering phenomena. After the FEOL MOSFETs had been fabricated, a Si3N4 ¬layer was deposited onto the wafer to act not only as a passivation layer of the FEOL devices but also an etching stopping layer which prevented the follow-up BOE solutions from damaging the underlying transistors. Before, during, and after the fabrication of the BEOL ZnO TFTs, we measured the characteristics of the PMOSFETs to confirm if the process steps have induced degradation on the PMOSFETs. The experimental results show no obvious differences between the results of measurements performed at various stages, confirming the feasibility of the low-temperature FPE scheme ( 350 ℃) for monolithic integration with the FEOL MOSFETs. We also fabricated and characterized two splits of FPE ZnO TFTs with discrete bottom-gate and common-gate configurations, respectively. The latter approach needs only one mask to complete the devices fabrication. Even though the discrete bottom-gate device undergoes a more complicated process in fabrication, on-off current ratio (ION/IOFF) is higher while the off-state leakage current of the device with discrete bottom-gate is greatly reduced as compared with the common-gate device owing to the significant decrease in the overlap area between the S/D regions and gate electrode.