標題: 基於快速傅立葉轉換多率訊號處理技術實現之低複雜度Quasi-ANSI濾波器組
FFT-Based Multirate Signal Processing for Low Complexity 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank
作者: 林欣垣
劉志尉
Lin, Hsin-Yuan
Liu, Chih-Wei
電子研究所
關鍵字: 多率濾波器組;助聽器濾波器組;實數訊號分頻處理;助聽器分頻系統;Quasi-ANSI filter bank;Multirate Signal Processin;Low Complexity Quasi-ANSI filter;Analysis filter bank for hearing aids
公開日期: 2017
摘要: 使用濾波器組在做訊號的分頻處理時,乘法佔了絕大部分的運算量,因此在動態功率的消耗上也佔了很大的比例,在這邊我們將系統轉換到頻域並運用循環摺積的方式代替一般的摺積運算做訊號處理,並結合頻域多率訊號處理的技術,使濾波器組在做運算時的乘法運算量能夠大幅降低。然而,當將系統轉換到頻域上做處理時,使用傳統的快速傅立葉轉換方式,整體系統而言,無法得到太大的乘法運算量下降。本論文中我們針對輸入訊號是實數這樣的特性下,引入了實數快速傅立葉轉換的演算法來代替原本的快速傅立葉轉換,我們實做了一個10.7毫秒延遲,18個次頻帶,1/3-octave quasi-ANSI 濾波器組架構。在這個的架構下,就每個輸出點而言,我們降低了54% 的運算複雜度。進一步的我們考慮了在頻域的系統下,我們能夠直接擷取截止頻帶內濾波器相對應的頻域係數,並與訊號相對應在頻域上的點做運算,對每個輸出點而言,我們成功的將運算複雜度再降低到70% 。我們將此架構實踐在TSMC 90奈米CMOS高臨界電壓製成單元庫(cell library),並且使用時脈閥(gated-clock)的技術。此硬體操作再取樣頻率為24KHz的速度下,並在時脈為13MHz的速度下工作,動態功率的消耗只有14μW,相對於已知的設計下,我們減少了77%的動態功率消耗。
When using filter bank to analyze signal, multiplication dominate most of computation complexity, it has an impact on dynamic power. In this thesis, instead of using linear convolution in time domain to analyze signal, we use circular convolution in frequency domain to implement filter bank. In this way, the computation complexity would be considerably reduced. However, it would not have obviously decreasing of the number of multiplication, if we using traditional fast fourier transform.。In this application, due to the input signal is real, we exploit real fast fourier transform(RFFT) to replace traditional fast fourier transform. We implement a 10.7-ms, 18-band, 1/3-octave quasi-ANSI filter bank in frequency domain. Comparing that with previous state-of-the-art design, the propose frequency domain quasi-ANSI filter bank saves approximately 54% computation complexity. Next, due to this system is in frequency domain, we could exactly know the region which are inside stopband of the filter. By only calculate the region which are inside stopband, we reduce more computation complexity successfully. For each output sample, it saves approximately 70% computation complexity。The proposed quasi-ANSI filter bank has been implemented in TSMC 90 nm CMOS high-VT technology and with gated-clock. The test chip can be operated at 13 MHz to real-time process 24 KHz audio and it consumes approximately 14 μW (@0.9V) dynamic power. Comparing with previous state-of-the-art design, this work saves approximately 77% of dynamic power.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450264
http://hdl.handle.net/11536/142860
顯示於類別:畢業論文