完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 林家名 | zh_TW |
dc.contributor.author | 許騰尹 | zh_TW |
dc.contributor.author | Lin, Jia Ming | en_US |
dc.contributor.author | Hsu, Terng-Yin | en_US |
dc.date.accessioned | 2018-01-24T07:42:46Z | - |
dc.date.available | 2018-01-24T07:42:46Z | - |
dc.date.issued | 2017 | en_US |
dc.identifier.uri | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070456142 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/142894 | - |
dc.description.abstract | 基於現今對於網路傳輸效率的需求,已投入眾多的人力資源於開發5G的系統規格上,而在5G逐見雛型的規格下,Soft-PHY成為未來系統架構的主流。此論文提出一個基於Soft-PHY的Multi Thread TX/RX PHY架構,在有pthread (POSIX threads)與GPU輔佐下使TX/RX PHY功能平行化運作,使得PHY能夠具有更高的吞吐量與更少的處理時間來加速其過程,本篇論文著重於pthread運作與驗證。 | zh_TW |
dc.description.abstract | Based on demand for network transmission, there has invested lots of resources to develop the specification of 5G. Due to the limitation of hardware, Soft PHY becomes more and more popular to implement PHY layer. In this paper, we propose a FDD’s multi-threading architecture based on Soft PHY to improve performance for whole eNB PHY layer. Using Pthread to cooperate with GPU and achieve multitasking for supporting multi users. Let PHY layer have more available CPU timing and much higher throughput to speed up. This paper focuses on the operation of Pthread and the verification of speedup for PHY uplink. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 執行緒 | zh_TW |
dc.subject | 長期演進技術 | zh_TW |
dc.subject | thread | en_US |
dc.subject | Long Term Evolution | en_US |
dc.title | 實作混合式執行緒架構於下行軟體實體層 | zh_TW |
dc.title | Hybrid-Threading Architecture for Soft-PHY Downlink | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |