以二氧化鋯作為閘極介電層之鍺金屬-氧化層-半導體電容器與N型金屬-氧化層-半導體電晶體之閘極工程研究

Abstract

在本篇論文中，我們首先針對使用氧化鉿和氧化鋯作為閘極介電層之金屬-氧化層-半導體電容結構作探討，從各種電容之電性結果分析，氧化鋯在作為閘極氧化層的應用上是更具潛力的。另外，我們也針對熱製程包括了沉積後退火和合金熱處理對於金屬-氧化層-半導體電容的影響做進一步的研究。對於沉積後退火製程來說，提高沉積後退火的溫度對於等效氧化層厚度的微縮相當有幫助，但介面的劣化是提高沉積後退火溫度時將會面臨的問題。然而，對於合金熱處理製程來說，在相對較低的溫度下，增加合金熱處理的時間是提升介面性質一個相當有效的方法。 接著，我們進一步針對不同結晶結構的氧化鋯之金屬-氧化層-半導體電容作探討。首先，我們可以發現5奈米的氧化鋯電容結構經過450度的沉積後退火下將發生相轉變的情形，而結晶之結構也由X光繞射技術確認為四方晶系之二氧化鋯，其擁有相當高之介電常數(37)，同時，其能隙也相較於其他的晶系結構更大，故應用在閘極氧化層上時，能得到最好之等效氧化層厚度對於閘極漏電流的特性。但是，遲滯現象和介面缺陷密度在結晶之後大幅劣化，這主要分別是源自於晶界的高密度缺陷和在結晶過程中，氧化鋯薄膜所造成之拉伸應力。 另外，N型鍺金屬-氧化層-半導體場效電晶體也作進一步作探討。其中，我們將討論包含了介面缺陷，邊緣缺陷，源極與汲極串聯阻抗對於電晶體之特性的影響。除此之外，我們也發現通道區域之摻雜濃度對於N型鍺金屬-氧化層-半導體場效電晶體的影響非常具大。最後，我們也根據不同結晶結構的二氧化鋯作為閘極氧化層之場效電晶體去做分析與討論，其各項電性結果皆非常接近，這說明了在使用結晶的氧化鋯作為閘極介電層的電晶體的元件中，因為介面特性大幅的改善，進一步提升N型鍺金屬-氧化層-半導體場效電晶體之電性表現。由這些電性結果，我們可以知道應用四方晶系二氧化鋯作為鍺金屬-氧化層-半導體場效電晶體之閘極氧化層是相當具有潛力的。

In this thesis, the MOSCAPs with the HfO2 and ZrO2 as gate dielectrics were firstly investigated. All of the electrical characteristics of the Zr-based samples imply that ZrO2 might be a promising material as the gate dielectric of Ge MOSFETs. Then, the effects of the thermal processes including the PMA and alloying processes on the Ge MOS capacitors were also briefly studied. It is believed that two-step annealing is necessary in order to achieve thin EOT. For the PMA process, the EOT takes advantages of the increase of the PMA temperature, but the interface properties sharply deteriorate when the PMA temperature is above 500 °C. In comparison, extending the period of the alloying process seems to be a good option for improving the Dit performance. After that, the MOSCAPs with different crystalline structures of the ZrO2 were examined. Consequently, the 5-nm-thick Zr-based sample with 450 °C PMA appears as the tetragonal phase, the k-value of which could achieve 37. Benefitting for the high dielectric constant and wide bandgap of the tetragonal ZrO2, the MIS device exhibits the best EOT-JG performance. However, the hysteresis and Dit characteristics sharply degrade owing to the high density of the electrical defects in the grain boundary and the stress generation of the ZrO2 film during the progress of the crystallization process, respectively. Additionally, the Ge n-MOSFETs were also investigated, and the degradation factors including the Nbt, Dit, and RS/D were discussed separately. Except for these factors, the Ni concentration is also considered as a crucial element to influence the performance of the Ge n-MOSFETs. Moreover, the Ge n-MOSFETs with different crystalline structures of ZrO2 as gate dielectrics were also studied. However, all of the electrical characteristics of these samples are resemble, indicating the well control of the interface properties of the crystallized samples. It has been shown to be feasible for the application of the tetragonal ZrO2 as the gate dielectric on the Ge MOSFETs.