應用於W頻帶的互補式金氧半製程之移相器設計

Abstract

此論文介紹一種數控式移相器的電路架構，並說明在毫米波訊號的應用中，移相器如何以積體電路形式實作。內文將分析移相器的操作原理與子電路的電路特性。本文使用台積電的65nm CMOS與40nm CMOS製程實作主動式數控寬帶移相器。電路工作於W頻段，橫跨77GHz至110GHz。移相器可由三位元的數位訊號以時序輸入的方式，在0˚至360˚之間可提供32個不同的相位延遲輸出，其輸出角度彼此間隔皆為11.25º。以40nm CMOS製程將移相器、混頻器、三倍頻器與中頻放大器整合為寬帶接收機。透過本文的接收機電路，可同時改變輸入訊號的相位延遲並且將頻率降至中頻，證明此電路的高整合度。最後以兩種不同的製程實作結果，討論移相器的電路特性以及不同子電路架構下的優缺點。

Architecture for digital-control phase shifters is introduced in this thesis. The implementation of the phase shifter in W-band integrated circuits is discussed. The operational principles of the phase shifter and the characteristics of the sub-circuits are examined. Two processes, TSMC 65nm-CMOS and TSMC 40nm-CMOS, are proposed to fabricate the phase shifter. The phase shifter fed with three-bit digital signals in time sequence can offers 32 phase delay outputs within the range from 0˚ to 360˚ in a step of 11.25˚. A broadband receiver comprising the phase shifter, a mixer, a tripler, and an IF amplifier was designed and fabricated in a single chip through the 40nm-version process. The receiver offers tunable phase delays and simultaneous down-conversion for the signals. This result demonstrates the feature of high integration of the proposed phase shifter. At the end, based on the fabrication results of the phase shifters by the two proposed processes, the advantages and disadvantages of their characteristics and associated sub-circuit structures are discussed.