應用於音頻的低功耗混合式類比數位轉換器

Abstract

隨著物連網的發展，生活中有越來越多可攜式的電子裝置。對攜帶式的裝置而言，降低功耗是一個很重要的難題。本文提出一個應用於音頻的混和式數位類比訊號轉換器，包含一個二階單位元的三角積分調變器(delta sigma modulator)及低精準度的連續漸進式類比數位轉換器(successive approximation register)。結合上述兩者的優點，實做出低功耗且高解析度的訊號轉換器。

為了節省功耗，本論文採用兩步式的轉換。此電路操作在1V的操作電壓下，先使用功耗轉換效率高的連續漸進式類比數位轉換器對訊號做粗略的量化，再將殘餘值饋入三角積分調變器進行處理。最後將兩者數位輸出經過整合，得到高解析度的結果。由於三角積分調變器處理的是殘餘值，對放大器的迴轉率(slew rate)要求較低，因此放大器可以設計的較省電，我們使用一級的放大器，希望能以較低的功耗達到所需的頻寬。同時因為三角積分調變器需要的輸入範圍較小，系統的動態範圍也能有所提升。

由於系統的解析度高，電容的不匹配效應會成為系統規格的限制。需要另外加入資料加權平均演算法(data weighted averaging)，將電容的非線性效應打散。而在電路實現上，電容陣列裡的單位電容總量需為二的冪次方，所以設計了一個非二進位的連續漸進式類比數位轉換器。

本電路以TSMC 90nm CMOS製程進行實作，配合Verilog AMS及Matlab模擬，取樣頻率為五百萬赫茲，處理的頻段為0到2000赫茲，超取樣率為125，在功耗210uW之下達到訊噪比103.35dB的成果。

With the rapid development of IOT (internet of things), there are more and more portable devices in our daily lives. Portable devices usually operate on batteries with little capacity, so reducing power consumption of these devices is a critical issue. This thesis proposed a hybrid ADC (analog to digital converter) applied in audio band, combining a 60 quantization levels SAR (successive approximation register) ADC with a second order single bit cascaded integrated feedforward DSM (delta sigma modulator). This hybrid ADC takes advantages of these two ADCs above to realize a low power and high resolution ADC.

To reduce power consumption, we employ two step conversion. First the input signal is processed by SAR ADC, which has high energy efficiency, to get coarse digital codes. Then we feed residue voltage into delta sigma modulator. The result of SAR ADC is used to adapt the reference voltage of delta sigma modulator. Finally, we get the high resolution result by combining digital codes from above two ADCs. Because residue voltage that delta sigma modulator processed is pretty low, relaxes the design specifications of OPAMP. Furthermore, dynamic range of delta sigma modulator can be increased.

Since linearity is a critical specification in our circuit design, which is mainly limited by capacitor mismatch in DAC, we use data weighted averaging technique to enhance DAC linearity. Circuit implementation of data weighted averaging makes the total number of unit capacitors in DAC to be power of two minus one, so we design a non-binary SAR ADC.

This work is simulated in 90nm TSMC CMOS process. The behavior model is verified by MATLAB and Verilog-AMS. Intended for audio applications, it achieves 103.35~dB peak SNR in a 20~KHz bandwidth, while dissipating 210 u W.