TaOx/TiO2雙氧化層電阻式記憶體於可撓式交錯矩陣結構與三維垂直式結構之應用

Abstract

隨著1965年摩爾(Gordon Earle Moore)所提出的摩爾定律，半導體元件持續微縮近半個世紀；近年來為了延續摩爾定律，科學家除了探討元件微縮，元件的多樣性也開始廣被討論，因此結合摩爾定律提出More Moore與More than Moore的概念。在記憶體元件領域中，2007年東芝所發表的3D-NAND快閃式記憶體認為是More Moore最具代表性的例子之一，透過垂直方向堆疊，提供更高的記憶密度以延續莫爾定律；另一方面，可撓式記憶體由於輕薄、製程成本低等優勢創造出全新應用領域，在More than Moore概念中逐漸受到關注。在未來More Moore與More than Moore 記憶體發展上，電阻式記憶體是最具潛力的前瞻式記憶體，因為它具有相容於積體電路製程、結構簡單、低溫製程及最小特徵面積4F2等優勢。 本篇論文主要探討一Ta/TaOx/TiO2/Ti雙氧化層電阻式記憶體，我們實現了可撓式交錯陣列結構，並且改善製程以實現在三維垂直結構上。在可撓式陣列的實驗中，製程溫度是影響可撓式元件的關鍵，因此我們探討不同的TiO2製程溫度對阻值切換的影響；我們發現隨著製程溫度的上升，高低阻值比越大。因此我們使用適當的TiO2製程溫度實現8×8可撓式交錯式陣列，並且進行可靠度分析，經過不同曲率與多次彎曲測試仍可保持穩定的特性。接著我們改善三維結構製程，三維垂直結構是由Ti下電極與SiO2絕緣層重覆堆疊，再經過垂直蝕刻後，在側壁上沉積氧化層、上電極，但Ti下電極容易氧化，下電極氧化嚴重影響三維結構的操作，因此我們選用不易氧化的TiN汰換Ti下電極；然而Ta/TaOx/TiO2/TiN結構卻無法實現阻值切換，因此我們透過製程的最佳化，在TiO2和TiN之間濺鍍一層富含氧缺的TiOx，並且定量的比較TiO2/TiOx/TiN與TiO2/TiN的蕭基能障(Schottky barrier)，我們發現TiO2/TiOx/TiN有效的降低蕭基能障並成功再現阻值切換特性，在Ta/TaOx/TiO2/TiOx/TiN元件中依然保有：(1)不需要生成燈絲路徑(Forming-free)，(2)自我限流(Self-compliance)，(3)穩定的阻態切換，(4)在±2V自我整流(Self-rectifying)超過四個數量級的優異特性。最後，我們嘗試使用原子層化學氣相沉積系統沉積雙氧化層，有別於真空濺鍍沉積系統，原子層化學氣相沉積有良好的覆蓋率有利於三維垂直側壁的沉積，並具有穩定的阻值切換特性。

Since Moore’s Law has proposed by Gordon E. Moore in 1965, the semiconductor devices have become smaller, denser, cheaper, and faster. His prediction has driven technology for a half century. However, recent miniaturization has become difficult when reaching the physical limits—the atomic scale. Hence, in order to prolong Moore’s Law, the concept of More Moore and More than Moore are proposed. For memory devices, one of the representative examples of More Moore is the BiCS 3D NAND memory demonstrated by Toshiba, which provides higher bit density to continue the Moore's law by using vertical stacking. For the More than Moore approach, flexible memories create new application spaces and have gained increasing attention recently. For the future More Moore and More than Moore memory development, resistive-switching random access memory (RRAM) is regarded as one of the most promising candidates for next-generation memory because of its process compatibility with standard VLSI processes, simple cell structure, low process temperature, small footprint of 4F2, etc. In this thesis, we focus on a promising Ta/TaOx/TiO2/Ti bilayer RRAM structure. We successfully fabricated RRAM array on a flexible substrate, and further optimized the process parameter for 3D vertical RRAM application. For the flexible RRAM, the process temperature is the main concern. We investigated the process temperature effect on the device switching characteristics. The result shows that increasing the TiO2deposition temperature improved the device switching characteristics. Therefore, an optimized deposition temperature for the flexible substrate was used to demonstrate a 8×8flexible crossbar array. The reliability test on the flexible array was also conducted. No significant performance degradation was found under bending. As for the 3D vertical RRAM structure, the Ti horizontal electrode located between the SiO2insulatinglayers is easily oxidized because of the high reactivity of Ti, which limits the minimal Ti thickness one can use and thus vertical scaling capability. Therefore, we explored the possibility of using TiN to replace the Ti electrode. However, the RRAM device completely lost its switching characteristics by using the TiN electrode. The switching characteristics can only be recovered by inserting a TiOx layer between TiO2and TiN. We found that the Schottky barrier at this interface is crucial for device performance. Our device with the TiN electrode shows superior characteristics, including: (1) forming free, (2) self-compliance,(3) small variability. (4) self-rectifying ratio higher than four orders of magnitudes at +/-2V. Finally, we attempted to deposit our film stack by using atomic layer deposition (ALD) instead of sputtering to achieve better film quality and step coverage. The preliminary results suggest this is a promising direction to pursue in the future.