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dc.contributor.author林育辰zh_TW
dc.contributor.author張俊彥zh_TW
dc.contributor.author林建中zh_TW
dc.contributor.authorLin, Yu-Chenen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.authorLin, Chien-Chungen_US
dc.date.accessioned2018-01-24T07:42:54Z-
dc.date.available2018-01-24T07:42:54Z-
dc.date.issued2016en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070258023en_US
dc.identifier.urihttp://hdl.handle.net/11536/143044-
dc.description.abstract本論文是已III-V材料InGaAs作為基板,透過矽基製程相同的技術去製作III-V半導體鰭式電晶體(Bulk III-V FinFET),並且開發所需關鍵技術包括: Al2O3/InXGa1-XAs高介電材料/金屬閘極技術、無金之源極/汲極接面技術、奈米三維InXGa1-XAs鰭式通道技術,最後在透過III-V 3D元件結構設計與模擬去驗證。本研究成果將可應用於未來次七奈米以下的低耗能異質三維電晶體開發與製作。 首先,我們介紹砷化銦鎵材料電容的製作流程,我們使用溼式化學溶液製程和原子層化學沉積的三甲基鋁氣體(Trimethyl Aluminum, TMA)的預先處理方式,對於改善Al2O3/InGaAs 介面品質是有不錯的效果。透過電容電壓(C-V)量測數據結合理論分析可以得知氧化鋁沉積在砷化銦鎵基板上的等效電容厚度(capacitance equivalent thickness,CET)大約6.91 nm,並採用電導法計算出界面缺陷電荷密度大約8×1011 /eVcm2,且可以由霍爾量測得知砷化銦鎵材料電子遷移率大約1630 cm²/V-s。 最後我們將最佳的電容特性應用在電晶體上,成功地製造出元件尺寸為通道寬度40 nm和閘極長度200 nm 的砷化銦鎵鰭式電晶體。為了使元件達到更佳的逆向偏壓特性,我們在通道層下方嵌入寬能隙材料砷化銦鋁當作阻擋層,因此在電性控制能力上有較佳的表現。此元件在驅動電壓為1.3伏特及汲極電壓為0.5伏特下,展現出大的驅動電流74.5 A/m,陡峭之次臨界擺幅為(Subthreshold swing, SS) 334 mV/dec、且此元件開關電流比(ION/IOFF ratio)大於102,薄片電阻(specific contact resistivity,ρc)為6.7×10-6 Ω-cm2 。zh_TW
dc.description.abstractA bulk InGaAs-based FinFET device compatible with Si-technology has been developed in this thesis. Here also applied several key techniques, including fabrication of Al2O3/InxGa1-xAs MOS, gold-free S/D contact, nano-scaled channel of InxGa1-xAs with 3D FinFET structure and the design simulation modeling of III-V 3D FinFET. All of the experimental results show these technologies could be utilized for low power consumption 3D transistor with dimension of less than 7nm. First, we studied the characteristics of InGaAs and Al2O3 by fabricating MOS capacitor. The capacitance equivalent thickness (CET) was about 6.91 nm by C-V measurement of Al2O3/InGaAs MOS capacitor. The Dit estimated by the conductance method was about 8×1011 /eVcm2. The electron mobility of InGaAs was about 1630 cm²/V-s by Hall measurement. Finally, InGaAs-based FinFET on InP substrate with back barrier layer was successfully fabricated. The dimension of the device has channel length of 40nm and gate length of 200nm, a wide band gap material of InAlAs as a barrier layer embedded in the back side of the channel for reducing current leakage of junction. The driving voltage of 1.3V and drain voltage of 0.5V, a high driving current of 74.5μA/μm, the subthreshold swing (SS) of about 334 mV/dec, the ION/IOFF ratio of about 102, and specific contact resistivity (ρc) of about 6.7×〖10〗^(-6) Ω-cm2 were achieved.en_US
dc.language.isoen_USen_US
dc.subject砷化銦鎵zh_TW
dc.subject鰭式電晶體zh_TW
dc.subject氧化鋁zh_TW
dc.subjectInGaAsen_US
dc.subjectFinFETen_US
dc.subjectAl2O3en_US
dc.title使用砷化銦鋁阻擋層與三氧化二鋁介電層於砷化銦鎵鰭式電晶體之電性研究zh_TW
dc.titleInvestigation of Electrical Characteristics on 100-nm InGaAs Channel FinFET Using InAlAs Back Barrier and Al2O3 Gate Dielectricen_US
dc.typeThesisen_US
dc.contributor.department光電系統研究所zh_TW
Appears in Collections:Thesis