以連續波雷射結晶之高性能多晶矽薄膜電晶體之研究

Abstract

近年來，低溫多晶矽技術應用在系統整合面板(System on Panels)及三維積體電路(Three-Dimensional Integrated Circuits)受到相當的矚目，在諸多低溫多晶矽薄膜結晶技術中又以連續波雷射結晶之低溫多晶矽薄膜晶粒及品質最為優異。然而連續波雷射結晶多晶矽薄膜之機制尚未清楚建立，因此本論文旨在研究以綠光連續波雷射結晶低溫多晶矽，藉由材料分析及薄膜電晶體之電特性，建立結晶之機制，並透過元件結構，探討雷射誘導之熱應力對元件特性之影響。 首先利用單次雷射掃描模式在石英基板上將非晶矽薄膜結晶為多晶矽探討其結晶機制，而所使用的雷射能量波型為高斯分布的橢圓雷射點，我們發現雷射結晶多晶矽薄膜與雷射能量分布呈現相關聯性。連續波雷射結晶多晶矽薄膜主要分為三個結晶區域，分別是高能量區域的中心結晶區間、中能量區域的過渡結晶區間及低能量區域的邊緣結晶區間。 在中心結晶區間，非矽薄膜受到大能量雷射施打，因此矽薄膜呈現全熔融，在雷射持續向前施打的同時，先前施打的熔融矽薄膜區域開始降溫固化，而之前固化的矽薄膜成為晶種誘導熔融區域結晶，因此結晶方向與雷射施打方向相同，結晶多晶矽薄膜之晶粒呈現長條狀大晶粒;過渡結晶區間，矽薄膜受中雷射能量施打造成部分熔融，除了先前施打後結晶矽薄膜所提供之晶種外，下方未熔融的非晶矽區域也同時提供晶種，此兩處的晶種會產生競爭，結晶晶粒也由靠近中心區間的長條橢圓結晶晶粒，轉換到靠近外側低能量的等軸性圓形晶粒;而邊緣結晶區間，低能量的雷射施打不能有效將矽薄膜熔融，因此非晶矽薄膜僅能藉由雷射能量進行固相結晶。 此三個不同區間受到施打能量不同，其多晶矽矽薄膜結晶晶粒大小及品質也有所不同。其中在中心區間高品質的多晶矽薄膜晶粒可成長到2 µm × 20 µm，而過渡區間與邊緣區間矽薄膜晶粒分別約為1 µm × 1 µm 與 50 nm × 50 nm。利用中心區間矽薄膜當作通道的n-type薄膜電晶體，其場效遷移率高達500 cm2V-1s-1，然而晶粒較小的過渡區間與邊緣區間，場效遷移率分別僅有278 cm2V-1s-1及48 cm2V-1s-1 之表現。藉由此結晶機制的建立，我們提出了重疊式掃描雷射結晶方式，以60 %重疊方式可以得到最佳品質之低溫多晶矽薄膜。 接著，為了更進一步提升元件特性及元件之間的均勻性，我們利用氮化矽側壁遮罩技術(Nitride Spacer Hard-Mask Technology)，製備三閘極奈米線薄膜電晶體(Tri-Gate Nanowire TFTs)，藉由微縮通道寬度，減低晶界缺陷之影響，並提升閘極控制能力。而此三閘極奈米線薄膜電晶體，其場效載子遷移率可高達900 cm2V-1s-1，臨界擺幅也降到269 mV/decade。而三閘極奈米線薄膜電晶體所表現出的超高場效載子遷移率，除了奈米線結構成功避開晶界缺陷外，連續波雷射結晶誘發伸張應力於多晶矽薄膜也有效提升載子遷移率。 為了更進一步了解雷射結晶所引導出的應力，我們藉由拉曼光譜分析及材料研究繞射儀(Materials Research Diffractometer, MRD)，了解應力在薄膜的分布情形並透過拉曼分析之公式估算與材料研究繞射儀之實際量測之應力大小，我們得知連續波雷射結晶矽薄膜的雙軸伸張熱應力高達近800 MPa；經由這些分析及先前文獻之探討，我們提出雷射結晶誘導之熱應力機制，主要發生原因為矽薄膜與底部二氧化矽薄膜之間的膨脹係數差。此外，我們利用包覆式閘極(Gate-All-Around)元件結構，藉以探討多晶矽奈米線薄膜電晶體在有無熱應力提升之特性差異，而包覆式閘極奈米現薄膜電晶體之場效載子遷移率達571 cm2V-1s-1，相較於三閘極奈米線薄膜電晶體，載子遷移率有所被弱化，主要是因為雷射誘導之熱應力在包覆式閘極元件結構下被大幅的釋放，因此載子遷移率無法被大幅提升。 而在先前之研究中，我們了解三閘極奈米線薄膜電晶體可成功降低晶界缺陷之影響並保留熱應力提升特性之優勢，但透過氮化矽側壁遮罩技術來完成元件製備是相當複雜的製備方式，因此我們也提出移動式光罩曝光技術，透過光罩與光罩之間相對位置差異，成功將i-line的曝光極限由350 nm推至100 nm，利用此簡單穩定的技術我們也製備了高性能三閘極奈米線薄膜電晶體。 最後，提出論文結論與針對未來研究可著重的工作方向。

Recently, low-temperature polycrystalline silicon (LTPS) technology has attracted increasing attention for the applications in the system on panels (SOPs) and three-dimensional integrated circuits (3-D ICs). Among those LTPS technologies, the polycrystalline silicon (poly-Si) film via the continuous-wave laser crystallization (CLC) exhibited the largest grain size and the best film quality. However, the crystallization mechanism of poly-Si film via CLC was not yet clarified. Therefore, in this dissertation, the high-crystallinity LTPS via the green CLC have been fabricated. Through the material analysis and device characteristics, the effect of the crystallization behavior and laser induced thermal strain have been realized. At first, the amorphous silicon (α-Si) films on the quartz wafers were crystallized with the single-scan mode of the green CLC. The spot profile of the continuous-wave (CW) laser beam was a Gaussian distribution; therefore the crystalline grain structure was varied at different laser energy positions. Therefore, the CLC poly-Si films via the single-scan mode could be clarified into three crystalline regions with different energy regions, including the center region, transition region, and edge region. In the center region, the α-Si thin films were fully molten under the CW laser irradiation, and the past annealing regions which have been solidified acted as the seeds and started to crystallize the molten silicon thin film. Thus, the grains of poly-Si at the center region were grown longitudinally along the laser scan direction. In the transition region, the α-Si film was partially molten. In addition to the past annealing regions of poly-Si films, the bottom of the unmolten silicon films in the bottom layer also as the seeds to crystallize the molten silicon thin films. Accordingly, the grain structure changed from medium polygonal morphologies around the center region to small equiaxial shapes near the edge region. As for the edge region the laser energy density was so low that the α-Si thin films only processed the solid-phase crystallization (SPC). Hence, only the small grains were formed in the edge region. The three region of CLC poly-Si film exhibited different grain size and quality. The grain size of high-quality poly-Si film in the center region was about 2 µm× 20µm, but the grain sizes of CLC poly-Si film in the transition and edge regions were about 1 µm × 1µm and 50 nm× 50 nm, respectively. The n-type poly-Si TFTs with the high-quality poly-Si films in the center region could achieve the field-effect mobility as high as 500 cm2V-1s-1, and the field-effect mobility of the poly-Si TFTs fabricated on the transition and edge regions were 278 and 48 cm2V-1s-1, correspondingly. It was because the grain sizes in the transition and edge regions were smaller than the center region ones. On the other hand, the multi-scan method was proposed to fabricate the high-quality polycrystalline silicon film, and the 60 % overlapping was the optimal condition to prepare the high-quality LTPS thin films. To further improve the device characteristics and device-to-device uniformity, the tri-gate nanowire TFTs via nitride hard-mask method have been proposed to reduce the grain boundary effects and enhance the gate controllability. Consequently, the CLC tri-gate nanowire TFTs exhibited the ultra-high field-effect mobility as high as 900 cm2V-1s-1. The subthreshold swing was as low as 269 mV/decade for the tri-gate structures. It was conjectured that the CW laser induced thermal tensile strain contributed to the enhancement of the device mobility. To further realize the laser induced thermal tensile strain, the Raman spectrum analysis and materials research diffractometer (MRD) were used to discuss the mechanism of the laser induced thermal tensile strain. The principal cause was the thermal expansion coefficient difference between Si and SiO2. From the calculation and MRD measured result, the thermal tensile stress of CLC poly-Si film was about 800 MPa. Furthermore, the gate-all-around (GAA) structure was also proposed to discuss the effect of thermal stress with device characteristics. The field-effect mobility of CLC GAA nanowire TFT was 571 cm2V-1s-1. As compared to the CLC tri-gate nanowire TFTs, the CLC GAA nanowire TFTs exhibited lower field-effect mobility than tri-gate ones. It was because of the GAA structure relaxed most of the laser induced stress. From the previous researches, we realized that the tri-gate structures could avoid grain boundary effects and maintain thermal strain effects. However, the nitride hard-mask method was too complex. For such a reason, a shift-mask method to improve the limitation of i-line stepper from 350 nm down to 100 nm was proposed. The high performance CLC tri-gate nanowire TFT with the channel width of 100 nm via shift-mask method were fabricated and discussed. Finally, the summary and conclusions as well as the prospects for the further researches were also proposed.