矽基板三五族高速電子元件的製程開發與研究

Abstract

本論文主旨在研製兩種三五族元件，分別為高電流氮化鎵(GaN)高速電子遷移率電晶體(HEMT)以及砷化銦鎵(InGaAs)鰭式電晶體(FinFET)。首先針對GaN-on-Si HEMT，藉由製程參數優化使源極與汲極的接觸電阻降低，並藉由拉長通道寬度(WG)與縮短閘極長度(LG)提升元件輸出電流密度。為製作可供快速充電器使用的功率元件，在光罩設計上以並聯線路製作指叉型HEMT。此外，為減低閘極漏電以及改善表面缺陷，在元件上使用原子層沉積系統(ALD)成長氧化鋁(Al2O3)介電質，研製出操作電流達8 A的GaN MIS-HEMT。第二部分著重在InGaAs FinFET的製程開發，整合CMOS元件製程，研製出In0.53Ga0.47As FinFET。本篇論文的實驗部分著重於金屬閘極的蝕刻製程，優化金屬閘極的側壁形貌，並有初步的元件電性表現。

In this thesis, we report two compound semiconductor devices: GaN-on-Si high electron mobility transistor (HEMT) and In0.53Ga0.47As-on-Si Fin field effect transistor (FinFET). We have demonstrated the high power GaN HEMT with metal-insulator-semiconductor (MIS) structure. We optimized process details, especially the thermal metallization process for low contact resistance of S/D Ohmic contacts. Furthermore, the interdigitated layout of GaN-on-Si HEMT was also introduced, corresponded to atomic layer deposition (ALD) process to obtain low gate leakage. Regarding the process optimization, the experimental results show that the 8 A of operation current for GaN-on-Si MIS-HEMT was successfully fabricated with 1000 V breakdown voltage and low gate leakage. We also developed the fabrication process of In0.53Ga0.47As FinFET on InP substrate. The top-down etching process was employed to fabricate InGaAs Fin structure. In addition, we optimized the metal gate etching process by modification of gas flow, ICP bias, and gas source. The final result shows that the additional nitrogen gas was required to obtain the vertical sidewall of TiN metal gate. The first demonstration of InGaAs FinFET was also fabricated, shows ~800 mA/mm of IDS at VGS = 2V. The subthreshold swing was calculated about 387 mV/dec, and the device leakage is essential to improve in the future. In summary, we built two basic process flows of III/V-on-Si devices. The III/V-on-Si device will be the candidate of the next generation electric transistors, leading to high power, high speed and low power consumption of high efficiency electronics.