三維電晶體由製程與長時間操作導致電特性變異 之多面向探討

Abstract

本篇論文闡述、發展並實作了有關金氧半互補式電晶體的電性變異性之理論、方法和應用。當元件持續微縮進入深奈米尺度後，金氧半互補式電晶體的電性變異(variability)已成一門顯學，針對雜質隨機分佈所致之擾動更引起廣大研究者的注目。然而，事實上，金氧半互補式電晶體還存在許多其他重要的因素導致電性的變異性卻很少被探討。電性變異性的來源可以略分為製程所致之變異性和長期操作所致之變異性兩大類：製程所致之變異性包含了已知的雜質隨機分佈所致之擾動、邊線不平整所致之擾動、閘極金屬多晶晶格大小不一致所致之擾動和薄膜表面粗糙所致之擾動；另一方面，長期操作所導致之擾動包含了隨機電報雜訊和隨機缺陷擾動兩大類。如果吾人欲設計一表現良好且可控之電子元件，則這些複雜的導致元件電性變異性之因子需要詳加研究與探討。

因此，在本篇論文，作者利用實驗方法詳加研究金氧半互補式電晶體之各種電性擾動並且建構一套簡單準確且可量化之理論及其相關方法論。在第二章，吾人開發出一種雜質的分佈剖面量測技術應用於研究雜質隨機分佈所致之擾動。由實際量測之數據，此技術能夠在通道隨機分佈的分立雜質的位置準確的定義出來，而使得吾人可藉此了解雜質在通道中真實的分佈狀態。在第三章，吾人再建構了一套隨機缺陷剖面的量測技術應用於研究在長期操作後導致的隨機缺陷之電性擾動現象。藉由此技術之實施，吾人可以了解非常小尺度的電晶體之閘極氧化層與其介面之缺陷分佈，進而使得關於金氧半互補式電晶體的長期操作後的可靠性議題可以被加以詳加探討，讓次世代之三維電晶體能夠擁有良好的可靠性之外亦能兼顧可被控制的電性擾動。 接下來，吾人於第四章進一步考察了另外一個在長期操作所導致的電性變異因子:隨機電報擾動。吾人實現了一種可以描繪導致隨機電報擾動缺陷的二維分佈之實驗技術，經由此一方法，吾人研究了多階層隨機電報擾動缺陷的機制與態樣，且更進一步地詳細分析了此種多階層隨機電報擾動的缺陷在靜態隨機存取記憶體之影響。 在研究了長期操作所致之電性變異因子和雜質隨機分佈所致之擾動之後，我們係世界首次針對三維電晶體之獨特的立體結構的側表面不平整性所致的電性變異性探討。為了研究立體結構的表面不平整性，吾人提出了一種簡單易行且低成本亦適合利用在大規模檢測之電性量測方法，利用此一量測技術吾人釐清了表面粗糙度(surface roughness)對電性變異性和元件的可靠性之關聯和影響。最後，所有的擾動因子都將反映在電晶體的驅動電流擾動上，更甚者，綜合表現於電路與系統架構上。 為了有系統地探討擾動因子對驅動電流之影響並對其建模，吾人使用了虛擬源極(VSM)的傳輸模型來對電晶體的基本汲極電流特性建模，接著引入了多變數分析之標準統計理論對複雜的擾動因子進行拆解，最終簡化出少數的關鍵決定擾動因子，而驅動電流之擾動可以透過這些少數關鍵決定的擾動因子進行近似並重建出簡單有效準確的統計模型，進而能夠預測並對所量得的實驗數據進行建模。透過這套方法論，吾人成功預測了反及閘、反或閘和反向器等電路之電性擾動模式。最終，透過對基本邏輯閘之電性擾動模式之分析，吾人提出了一簡單可預測且準確之半經驗公式而能夠應用於超大型積體電路之電性擾動。

在本論文得出的結果和成果將對於三維電晶體與相關電路設計的深入了解和指引能夠成功量產製造此元件的重要方向，有很大的幫助，而這其中亦產生了許多有用的創新與應用價值。

Theories, methodolgies, and applications of variabilities for CMOS devices have been elucidated, developed, and implemented. The variation of CMOS devices has been a significant issue as the devices are continuously scaled, in particular into the deep nano regime. The random dopant fluctuation(RDF) has become the most important issue that has received much more attentions more recently. However, there are other important factors that have seldomly been investigated. The variation-sources can be categorized into the process-induced and the stress-induced variations. The process-induced variations include the well-known RDF, the work function fluctuation(WFF) induced by un-uniform metal-grain-size, the line-edge-roughness(LER) induced by un-accurately exposed lithography, and the roughly deposited ultra-thin induced surface roughness variation(SRV); on the other hand, the stress induced variation considers the long-term-stress induced electric variations, including the random telegraph noise(RTN) induced by the interaction between the bulk traps and the channel carriers and by the random dopant fluctuation(RTF) induced by the disturbance of the interface traps. If one would like to design well-behaved and easily predictable devices, these various variation sources should be well-understood and under control.

Therefore, in this dissertation, the author has dedicated to the investigations of the variabilities of CMOS devices by using experimental methods so as to construct a simple, accurate, and the quantifiable theory and its methodology. In the chapter 2, the RDF has been thoroughly studied thourgh the profiling of the random-trap distribution along the channel direction by the discrete-dopant profiling technqiue. The discrete dopant profiling technique is based on the real measured data so as to directly sense the locations of the discrete dopants, which enables us to undertand the real distribution of the random dopants. In the chapter 3, the RTF has been examined for the devices after long-term stresses by the radom trap profiling technqiue. By using this technique, the profile of stress-induced traps can be mapped along the channel direction in ultra-scaled devices. This techniquie has earned a successful applictaion to the reliability study of the trigate CMOS devices, which makes it possible to design the next-generation trigate devcies with controlled variability and acceptable reliability. Furthmore, in the chapter 4, another big issue of variabilities after long-term stresses, that is, the random telegraph noise has been also carefully studied by using the 2D RTN profiling techniquie. With assistance of this techniquie, the 2D potential of RTN traps have been first employed. Morever, by using this techniquie, we can decouple the multi-level RTN signals into two interacting 2-level RTN traps and separatedly and individually study their characteristics. Finally, the impacts of multi-level RTN on the supressed window of the transfer curves for SRAM cells have induced as a new mechanism of the failure of transition in SRAM cells. In addition to the general variation issues of CMOS devices, such as RDF, RTF, and RTN, there is another important variation source in consideration of the unique 3D strucuture of trigate devices, that is, the surface roughness variation(SRV) because of the rough sidewall of the fins. In order to interpret the rough degree of the fin surfaces for a larger amount of devices statisitcally, an easy and usefull techniquie has been deduced and applied to extract the degree of surface roughness by using the concept of the gate-current variation for the first time in the word. The results have shown that the trigate devices with taller fin hieght have suffered much serious issues of surface roughness variation, which hurts the Vth variation and degrades the life-time of devices during stresses. Finally, all the viariation sources will reflect to the drian current of devices and its behaviours at the circuit level. In the end of this dissertation, the virtual source model has been involved to model the drain current in Id-Vgs and Id-Vds. Moreover, we have introduced the multi-variate analysis method to decompose the variations of drain current into few important factors, and by dealing with the variations of those individual affecting factors, the variation of drain currernt can be re-constructed in terms of a simple statistical expression so as to predict and to model the measured data. In this methodology, we construct the models of each drain current variation on each device and then the circuit level variation of basic logic gates, such as NAND, NOR, Inverter etc. via the commercially available Spice software. And finally, a simple, predictable, and accurate qusai-empirical fomula can be generalized to well predict the variation of very-large scale CMOS integrated ciruit.

These results and achievements obtained in this dissertation will help on the understanding of trigate devices as well as providing several important directions to the manufacturing of such devices. Innovations and applications have been accomplished in this systemtic study.