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dc.contributor.authorHsieh, E. Rayen_US
dc.contributor.authorKuo, Yen Chenen_US
dc.contributor.authorCheng, Chih-Hungen_US
dc.contributor.authorKuo, Jing Lingen_US
dc.contributor.authorJiang, Meng-Ruen_US
dc.contributor.authorLin, Jian-Lien_US
dc.contributor.authorChen, Hung-Wenen_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorLiu, Chuan-Hsien_US
dc.contributor.authorChen, Tse Puen_US
dc.contributor.authorHuang, Shih Anen_US
dc.contributor.authorChen, Tai-Juen_US
dc.contributor.authorCheng, Osberten_US
dc.date.accessioned2018-08-21T05:53:03Z-
dc.date.available2018-08-21T05:53:03Z-
dc.date.issued2017-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2017.2763960en_US
dc.identifier.urihttp://hdl.handle.net/11536/144215-
dc.description.abstractIn this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 degrees C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory.en_US
dc.language.isoen_USen_US
dc.subjectEmbedded memoryen_US
dc.subjectFinFETen_US
dc.subjecthigh-k metal gateen_US
dc.subjectRRAMen_US
dc.subjectsneak pathen_US
dc.subjectMoore's gapen_US
dc.titleA 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Pathen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2017.2763960en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume64en_US
dc.citation.spage4910en_US
dc.citation.epage4918en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000417727500015en_US
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