完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Chang, Chia-Hung | en_US |
dc.contributor.author | Chen, Wei-Hsien | en_US |
dc.contributor.author | Gong, Cihun-Siyong Alex | en_US |
dc.contributor.author | Hu, Wei-Wen | en_US |
dc.date.accessioned | 2018-08-21T05:53:04Z | - |
dc.date.available | 2018-08-21T05:53:04Z | - |
dc.date.issued | 2017-12-01 | en_US |
dc.identifier.issn | 0098-9886 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1002/cta.2370 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144241 | - |
dc.description.abstract | A direct conversion transmitter with auto-calibration mechanism is presented in this paper. Both the carrier leakage and in-phase/quadrature (I/Q) phase imbalance are compensated by a proposed calibration algorithm to improve transmitter's single-sideband performance. The digital-assisted correction circuits are implemented in a calibration feedback path to reduce the mismatches and variations, which in turn achieves properties of high linearity, high sideband, and carrier suppression ratio. The measured single-sideband performance with calibration applied to the transmitter demonstrates an over 40 and 50-dBc rejection on sideband and carrier signals at the desired frequency band, respectively. For linearity performance, the measured output 1-dB compression point (OP1dB) is 9.1dBm, while the highest voltage gain is from 4.3 to 6.2dB. Additionally, the error vector magnitude (EVM) of -37.082dB (< 1.4%) can be achieved under an orthogonal frequency division multiple access (OFDMA) 64 QAM-3/4 modulated signal test. The transmitter consumes 112.7mA under supply voltage of 3.3V using the TSMC SiGe BiCMOS technology. Copyright (c) 2017 John Wiley & Sons, Ltd. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | direct conversion | en_US |
dc.subject | calibration | en_US |
dc.subject | carrier leakage | en_US |
dc.subject | I | en_US |
dc.subject | Q mismatch | en_US |
dc.subject | transmitter | en_US |
dc.title | A direct conversion transmitter with digital-assisted DC offset and I/Q phase calibration | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1002/cta.2370 | en_US |
dc.identifier.journal | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | en_US |
dc.citation.volume | 45 | en_US |
dc.citation.spage | 2073 | en_US |
dc.citation.epage | 2084 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000418158100011 | en_US |
顯示於類別: | 期刊論文 |