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dc.contributor.authorLin, M. H.en_US
dc.contributor.authorLin, Y. C.en_US
dc.contributor.authorLin, Y. S.en_US
dc.contributor.authorSun, W. J.en_US
dc.contributor.authorChen, S. H.en_US
dc.contributor.authorChiu, Y. C.en_US
dc.contributor.authorCheng, C. H.en_US
dc.contributor.authorChang, C. Y.en_US
dc.date.accessioned2018-08-21T05:53:08Z-
dc.date.available2018-08-21T05:53:08Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn2162-8769en_US
dc.identifier.urihttp://dx.doi.org/10.1149/2.0261704jssen_US
dc.identifier.urihttp://hdl.handle.net/11536/144305-
dc.description.abstractWe investigated an N-type III-V FinFET with a 25-nm In0.53Ga0.47As channel and a 300-nm In0.52Al0.48As barrier layer on an InP substrate. The In0.52Al0.48As barrier layer is used to suppress leakage current from the InP substrate and the 10-nm Al2O3 film deposited by atomic layer deposition (ALD) can be a robust gate dielectric to mitigate interface traps. The on to off current ratio is approximately three orders of magnitude, the subthreshold swing (SS) is 350 mV/dec, and the maximum driving current density is 130 mu A/mu m at V-G = 1.5 V for InGaAs FinFET with a fin width of 40 nm and gate length of 200 nm. (c) 2017 The Electrochemical Society. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleInvestigation of Electrical Characteristics on 25-nm InGaAs Channel FinFET Using InAlAs Back Barrier and Al2O3 Gate Dielectricen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/2.0261704jssen_US
dc.identifier.journalECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGYen_US
dc.citation.volume6en_US
dc.contributor.department光電系統研究所zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentInstitute of Photonic Systemen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000418886800011en_US
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