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dc.contributor.authorShen, Wen-Weien_US
dc.contributor.authorChang, Hsiao-Chunen_US
dc.contributor.authorYang, Yu-Taoen_US
dc.contributor.authorHu, Yu-Chenen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:53:17Z-
dc.date.available2018-08-21T05:53:17Z-
dc.date.issued2018-02-01en_US
dc.identifier.issn2156-3950en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCPMT.2017.2775861en_US
dc.identifier.urihttp://hdl.handle.net/11536/144490-
dc.description.abstractAlthough chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of mu-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.en_US
dc.language.isoen_USen_US
dc.subject3-D heterogeneous integrationen_US
dc.subjectdouble-self-assembly technologyen_US
dc.titleUneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integrationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCPMT.2017.2775861en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGYen_US
dc.citation.volume8en_US
dc.citation.spage310en_US
dc.citation.epage316en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000424515100017en_US
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