完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, P. H. | en_US |
dc.contributor.author | Peng, K. P. | en_US |
dc.contributor.author | Lin, H. C. | en_US |
dc.contributor.author | George, T. | en_US |
dc.contributor.author | Li, P. W. | en_US |
dc.date.accessioned | 2018-08-21T05:53:27Z | - |
dc.date.available | 2018-08-21T05:53:27Z | - |
dc.date.issued | 2018-05-18 | en_US |
dc.identifier.issn | 0957-4484 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1088/1361-6528/aab17b | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144704 | - |
dc.description.abstract | We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5-95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5-4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1-xGex shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1-xGex shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | MOS | en_US |
dc.subject | germanium quantum dot | en_US |
dc.subject | SiGe | en_US |
dc.subject | self-organization | en_US |
dc.subject | channel engineering | en_US |
dc.subject | strain engineering | en_US |
dc.title | Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1088/1361-6528/aab17b | en_US |
dc.identifier.journal | NANOTECHNOLOGY | en_US |
dc.citation.volume | 29 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000427876700001 | en_US |
顯示於類別: | 期刊論文 |