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dc.contributor.authorLiu, Po-Tsunen_US
dc.contributor.authorChang, Chih-Hsiangen_US
dc.contributor.authorKuo, Po-Yien_US
dc.contributor.authorChen, Po-Wenen_US
dc.date.accessioned2018-08-21T05:53:27Z-
dc.date.available2018-08-21T05:53:27Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2162-8769en_US
dc.identifier.urihttp://dx.doi.org/10.1149/2.0221802jssen_US
dc.identifier.urihttp://hdl.handle.net/11536/144720-
dc.description.abstractThis study investigates the effects of positive gate-bias stress (PGBS) on the electrical instability of amorphous InWO/InGaZnO (a-IWO/IGZO) stacked thin-film transistors (TFTs) with a backchannel passivation layer of SiO2 or Al2O3 film. After the application of PGBS to a-IWO/IGZO TFTs with an SiO2 passivation layer, abnormal negative threshold voltage (Vth) shifts were observed, while positive Vth shifts were observed in the TFTs with an Al2O3 passivation layer. This unusual positive bias instability is explained using a two-step electrical degradation behavior model, including both electron trapping and moisture absorption at the damaged back channel interface between a-IWO/IGZO TFTs and the SiO2 passivation layer. (C) 2018 The Electrochemical Society.en_US
dc.language.isoen_USen_US
dc.titleEffects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/2.0221802jssen_US
dc.identifier.journalECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGYen_US
dc.citation.volume7en_US
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000428118600017en_US
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