完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Po-Tsun | en_US |
dc.contributor.author | Chang, Chih-Hsiang | en_US |
dc.contributor.author | Kuo, Po-Yi | en_US |
dc.contributor.author | Chen, Po-Wen | en_US |
dc.date.accessioned | 2018-08-21T05:53:27Z | - |
dc.date.available | 2018-08-21T05:53:27Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.issn | 2162-8769 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1149/2.0221802jss | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144720 | - |
dc.description.abstract | This study investigates the effects of positive gate-bias stress (PGBS) on the electrical instability of amorphous InWO/InGaZnO (a-IWO/IGZO) stacked thin-film transistors (TFTs) with a backchannel passivation layer of SiO2 or Al2O3 film. After the application of PGBS to a-IWO/IGZO TFTs with an SiO2 passivation layer, abnormal negative threshold voltage (Vth) shifts were observed, while positive Vth shifts were observed in the TFTs with an Al2O3 passivation layer. This unusual positive bias instability is explained using a two-step electrical degradation behavior model, including both electron trapping and moisture absorption at the damaged back channel interface between a-IWO/IGZO TFTs and the SiO2 passivation layer. (C) 2018 The Electrochemical Society. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/2.0221802jss | en_US |
dc.identifier.journal | ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY | en_US |
dc.citation.volume | 7 | en_US |
dc.contributor.department | 光電工程學系 | zh_TW |
dc.contributor.department | Department of Photonics | en_US |
dc.identifier.wosnumber | WOS:000428118600017 | en_US |
顯示於類別: | 期刊論文 |