完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shen, Chiuan-Huei | en_US |
dc.contributor.author | Kuo, Po-Yi | en_US |
dc.contributor.author | Chung, Chun-Chih | en_US |
dc.contributor.author | Lee, Sen-Yang | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.date.accessioned | 2018-08-21T05:53:29Z | - |
dc.date.available | 2018-08-21T05:53:29Z | - |
dc.date.issued | 2018-04-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2018.2810846 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144758 | - |
dc.description.abstract | In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility mu FE compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high I-ON/I-OFF current ratio of 1.1 x 10(7). The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an I-ON/I-OFF current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for futuremonolithic 3D integrated-circuit applications. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Crystallinity | en_US |
dc.subject | poly-Si | en_US |
dc.subject | rapid thermal annealing | en_US |
dc.subject | stack multi-channels | en_US |
dc.subject | trigate | en_US |
dc.title | Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2018.2810846 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 39 | en_US |
dc.citation.spage | 512 | en_US |
dc.citation.epage | 515 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000428689000013 | en_US |
顯示於類別: | 期刊論文 |