完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Chien-Hui | en_US |
dc.contributor.author | Wen, Charles H. -P. | en_US |
dc.date.accessioned | 2018-08-21T05:53:42Z | - |
dc.date.available | 2018-08-21T05:53:42Z | - |
dc.date.issued | 2018-06-01 | en_US |
dc.identifier.issn | 1943-0663 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LES.2017.2776292 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145041 | - |
dc.description.abstract | Hotspots occur frequently in 3-Dmulticore processors (3D-MCPs) and they may adversely impact the reliability of the system and its lifetime. We present support-vector-machine (SVM)-based dynamic voltage assignment (SVMDVA) strategy to select voltages among low-power and high-performance operating modes for reducing hotspots and optimizing performance in 3D-MCPs. The proposed SVMDVA can be employed in online, thermally constrained task schedulers. First, we revealed two different thermal regions of 3D-MCPs and extract different key features of these regions. Based on these key features, SVM models are constructed to predict the thermal behavior and the best operation mode of 3D-MCPs during runtime. SVMDVA using SVM models with monitoring workload and temperature behavior can effectively limit the temperature increase in 3D-MCPs. This is extremely important for accurately predicting the thermal behavior and providing the optimum operating condition of 3D-MCPs to achieve the best system performance. Experimental results show that SVMDVA is an effective technique for reducing hotspot occurrences (57.19%) and increasing throughput (25.41%) for 3D-MCPs. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 3-D multicore processors (3D-MCPs) | en_US |
dc.subject | dynamic voltage and frequency scaling (DVFS) | en_US |
dc.subject | hotspots | en_US |
dc.subject | online task scheduler | en_US |
dc.subject | support vector machine (SVM) | en_US |
dc.subject | voltage assignment | en_US |
dc.title | SVM-Based Dynamic Voltage Prediction for Online Thermally Constrained Task Scheduling in 3-D Multicore Processors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LES.2017.2776292 | en_US |
dc.identifier.journal | IEEE EMBEDDED SYSTEMS LETTERS | en_US |
dc.citation.volume | 10 | en_US |
dc.citation.spage | 49 | en_US |
dc.citation.epage | 52 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000433336000005 | en_US |
顯示於類別: | 期刊論文 |