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dc.contributor.authorLi, Yi-Shaoen_US
dc.contributor.authorWu, Chun-Yien_US
dc.contributor.authorChou, Chia-Hsinen_US
dc.contributor.authorLiao, Chan-Yuen_US
dc.contributor.authorChuang, Kai-Chien_US
dc.contributor.authorLuo, Jun-Daoen_US
dc.contributor.authorLi, Wei-Shuoen_US
dc.contributor.authorCheng, Huang-Chungen_US
dc.date.accessioned2018-08-21T05:53:43Z-
dc.date.available2018-08-21T05:53:43Z-
dc.date.issued2018-06-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.57.06KB06en_US
dc.identifier.urihttp://hdl.handle.net/11536/145055-
dc.description.abstractA tetraethyl-orthosilicate (TEOS) capping oxide was deposited by low-pressure chemical vapor deposition (LPCVD) on a 200-nm-thick amorphous Si (a-Si) film as a heat reservoir to improve the crystallinity and surface roughness of polycrystalline silicon (poly-Si) formed by continuous-wave laser crystallization (CLC). The effects of four thicknesses of the capping oxide layer to satisfy an antireflection condition, namely, 90, 270, 450, and 630 nm, were investigated. The largest poly-Si grain size of 2.5 x 20 mu m(2) could be achieved using a capping oxide layer with an optimal thickness of 450 nm. Moreover, poly-Si nanorod (NR) thin-film transistors (TFTs) fabricated using the aforementioned technique exhibited a superior electron field-effect mobility of 1093.3 cm(2) V-1 s(-1) and an on/off current ratio of 2.53 x 10(9). (c) 2018 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleEffects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallizationen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/JJAP.57.06KB06en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume57en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000433573000015en_US
Appears in Collections:Articles