完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, Yi-Juen_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.date.accessioned2018-08-21T05:53:52Z-
dc.date.available2018-08-21T05:53:52Z-
dc.date.issued2018-08-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.57.084201en_US
dc.identifier.urihttp://hdl.handle.net/11536/145257-
dc.description.abstractThe effects of the Si-1-xGe(x) epitaxial tunnel layer (ETL) scheme and ETL thickness on the ON-state current (l(ON)) of Si-1_Ge-x(x) ETL tunnel field-effect transistors (TFETs) are thoroughly studied in this work. Compared with using pure Ge as the ETL, implementing Si1-xGex with linearly changing Ge content degrades l(ON) markedly, whereas using Si1-xGex with stepwise changing Ge content degrades l(ON) slightly. Although changing the ETL material from Ge to Si1-xGex leads to l(ON) reduction, for practical implementation, it is anticipated that a better subthreshold swing (SS) can be obtained by ETL crystal quality improvement. The best Si1-xGex ETL scheme for application in complementary Si1-xGex ETL TFETs is 4-nm-thick Si1-xGex with stepwise decreasing bandgap (E-g).( )It is believed that this structure is more promising for implementation. (C) 2018 The Japan Society of Applied Physics.en_US
dc.language.isoen_USen_US
dc.titleBandgap engineering of Si1-xGex epitaxial tunnel layer for tunnel FETsen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/JJAP.57.084201en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume57en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000438602100001en_US
顯示於類別:期刊論文