完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Yi-Ju | en_US |
dc.contributor.author | Tsui, Bing-Yue | en_US |
dc.date.accessioned | 2018-08-21T05:53:52Z | - |
dc.date.available | 2018-08-21T05:53:52Z | - |
dc.date.issued | 2018-08-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.7567/JJAP.57.084201 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145257 | - |
dc.description.abstract | The effects of the Si-1-xGe(x) epitaxial tunnel layer (ETL) scheme and ETL thickness on the ON-state current (l(ON)) of Si-1_Ge-x(x) ETL tunnel field-effect transistors (TFETs) are thoroughly studied in this work. Compared with using pure Ge as the ETL, implementing Si1-xGex with linearly changing Ge content degrades l(ON) markedly, whereas using Si1-xGex with stepwise changing Ge content degrades l(ON) slightly. Although changing the ETL material from Ge to Si1-xGex leads to l(ON) reduction, for practical implementation, it is anticipated that a better subthreshold swing (SS) can be obtained by ETL crystal quality improvement. The best Si1-xGex ETL scheme for application in complementary Si1-xGex ETL TFETs is 4-nm-thick Si1-xGex with stepwise decreasing bandgap (E-g).( )It is believed that this structure is more promising for implementation. (C) 2018 The Japan Society of Applied Physics. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Bandgap engineering of Si1-xGex epitaxial tunnel layer for tunnel FETs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.7567/JJAP.57.084201 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
dc.citation.volume | 57 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000438602100001 | en_US |
顯示於類別: | 期刊論文 |