完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Wen-Hsiang | en_US |
dc.contributor.author | Lin, Chien-Hsueh | en_US |
dc.contributor.author | Mu, Szu-Pang | en_US |
dc.contributor.author | Chen, Li-De | en_US |
dc.contributor.author | Tsai, Cheng-Hong | en_US |
dc.contributor.author | Chiu, Yen-Chih | en_US |
dc.contributor.author | Chao, Mango C. -T. | en_US |
dc.date.accessioned | 2018-08-21T05:54:26Z | - |
dc.date.available | 2018-08-21T05:54:26Z | - |
dc.date.issued | 2017-08-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2017.2648842 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145953 | - |
dc.description.abstract | As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electromigration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Electro-migration (EM) | en_US |
dc.subject | IR drop | en_US |
dc.subject | machine learning | en_US |
dc.subject | power grid design | en_US |
dc.subject | routing cost model | en_US |
dc.subject | routing-driven | en_US |
dc.title | Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2017.2648842 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 36 | en_US |
dc.citation.spage | 1237 | en_US |
dc.citation.epage | 1250 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000408147200001 | en_US |
顯示於類別: | 期刊論文 |