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dc.contributor.authorWu, Chih-Chiangen_US
dc.contributor.authorJeng, Shyr-Longen_US
dc.date.accessioned2019-04-03T06:43:58Z-
dc.date.available2019-04-03T06:43:58Z-
dc.date.issued2017-08-01en_US
dc.identifier.issn2073-4352en_US
dc.identifier.urihttp://dx.doi.org/10.3390/cryst7080250en_US
dc.identifier.urihttp://hdl.handle.net/11536/145973-
dc.description.abstractThis paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT). Using the JFET to simulate the MIS-HEMT not only ensures that the curve fits an S-shape transfer characteristic but also enables the pinch-off voltages extracted from the threshold voltage of the MIS-HEMT to be used as a watershed to distinguish where the drop in parasitic capacitance occurs. Parameter extraction was based on static and dynamic characteristics, which involved simulating the behavior of the created GaN FET model and comparing the extracted parameters with experimental measurements to demonstrate the accuracy of the simulation program with an integrated circuit emphasis (SPICE) model. Cascode capacitance was analyzed and verified through experimental measurements and SPICE simulations. The analysis revealed that the capacitance of low-voltage MOSFETs plays a critical role in increasing the overall capacitance of cascode GaN FETs. The turn-off resistance mechanism effectively described the leakage current, and a double-pulse tester was used to evaluate the switching performance of the fabricated cascode GaN FET. LTspice simulation software was adopted to compare the experimental switching results. Overall, the simulation results were strongly in agreement with the experimental results.en_US
dc.language.isoen_USen_US
dc.subjectGaN FETen_US
dc.subjectMIS-HEMTen_US
dc.subjectcascodeen_US
dc.subjectbehavioral modelen_US
dc.subjectparasitic capacitanceen_US
dc.subjectturn-off resistanceen_US
dc.subjectSPICEen_US
dc.titleSimulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.3390/cryst7080250en_US
dc.identifier.journalCRYSTALSen_US
dc.citation.volume7en_US
dc.citation.issue8en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department機械工程學系zh_TW
dc.contributor.departmentDepartment of Mechanical Engineeringen_US
dc.identifier.wosnumberWOS:000408374200022en_US
dc.citation.woscount2en_US
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