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dc.contributor.authorHong, Kuo-Cheen_US
dc.contributor.authorChiueh, Hermingen_US
dc.date.accessioned2014-12-08T15:20:30Z-
dc.date.available2014-12-08T15:20:30Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-6470-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/14608-
dc.description.abstractA wide-bandwidth low-power CT Sigma Delta modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 mu m CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time deviator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.en_US
dc.language.isoen_USen_US
dc.titleA 36-mW Continuous-Time Sigma-Delta Modulator with 74db Dynamic Range and 10-MHz Bandwidthen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIPen_US
dc.citation.spage392en_US
dc.citation.epage395en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000295220400069-
Appears in Collections:Conferences Paper