Full metadata record
DC FieldValueLanguage
dc.contributor.authorSung, Wen-Lien_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2018-08-21T05:56:25Z-
dc.date.available2018-08-21T05:56:25Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn1944-9399en_US
dc.identifier.urihttp://hdl.handle.net/11536/146176-
dc.description.abstractWe perform experimentally validated statistical device simulation to explore characteristic fluctuation induced by random discrete dopants (RDDs) inside the source / drain extensions of undoped gate-all-around silicon nanowire MOSFETs. The engineering findings of this study indicate that both the DC and dynamic characteristic fluctuation caused by RDDs of the drain extension has relatively smaller variability than that caused by RDDs of the source extension. It could be attributed to the effect of random position of RDDs appearing in the source / drain extensions. Compared to RDDs of the source extension, fluctuations of voltage gain and cut-off frequency of the explored gate-all-around silicon nanowire MOSFET circuit induced by RDDs of the drain extension can be significantly reduced from 24.3% and 20.7% to 0.9% and 2.2%, respectively.en_US
dc.language.isoen_USen_US
dc.titleAsymmetric Characteristic Fluctuation of Undoped Gate-All-Around Nanowire MOSFETs Induced by Random Discrete Dopants inside Source/Drain Extensionsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE 17TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)en_US
dc.citation.spage101en_US
dc.citation.epage104en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電機工程學系zh_TW
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000434647500023en_US
Appears in Collections:Conferences Paper