A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, Bo-Wei	en_US
dc.contributor.author	Wang, Jen-Peng	en_US
dc.contributor.author	Tsai, Chia-Ming	en_US
dc.date.accessioned	2018-08-21T05:56:32Z	-
dc.date.available	2018-08-21T05:56:32Z	-
dc.date.issued	2010-01-01	en_US
dc.identifier.uri	http://hdl.handle.net/11536/146307	-
dc.description.abstract	A high speed, low delay/log(Delta Vin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(Delta Vin) of the comparator is 22ps/dec and consumes 213 mu W at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.	en_US
dc.language.iso	en_US	en_US
dc.subject	Comparator	en_US
dc.subject	negative resistance	en_US
dc.subject	transconductance boosting	en_US
dc.title	A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS)	en_US
dc.citation.spage	648	en_US
dc.citation.epage	651	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000296009300164	en_US
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