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dc.contributor.authorKanda, T.en_US
dc.contributor.authorZade, D.en_US
dc.contributor.authorLin, Y. -C.en_US
dc.contributor.authorKakushima, K.en_US
dc.contributor.authorAhmet, P.en_US
dc.contributor.authorTsutsui, K.en_US
dc.contributor.authorNishiyama, A.en_US
dc.contributor.authorSugii, N.en_US
dc.contributor.authorChang, E. Y.en_US
dc.contributor.authorNatori, K.en_US
dc.contributor.authorHattori, T.en_US
dc.contributor.authorIwai, H.en_US
dc.date.accessioned2018-08-21T05:56:32Z-
dc.date.available2018-08-21T05:56:32Z-
dc.date.issued2011-01-01en_US
dc.identifier.issn1938-5862en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.3567624en_US
dc.identifier.urihttp://hdl.handle.net/11536/146316-
dc.description.abstractThe electrical characteristics of InGaAs MOS capacitors with 8-nm-thick La2O3 gate dielectrics have been measured. The effects of annealing temperature and annealing time on the interface state densities (D-it) have been extracted. It has been found that the low Dit can be achieved by lowering the annealing temperature for an extended period of time.en_US
dc.language.isoen_USen_US
dc.titleAnnealing Effect on the Electrical Properties of La2O3/InGaAs MOS Capacitorsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1149/1.3567624en_US
dc.identifier.journalCHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011)en_US
dc.citation.volume34en_US
dc.citation.spage483en_US
dc.citation.epage487en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000300456600074en_US
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