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dc.contributor.authorChen, Hung-Kaien_US
dc.contributor.authorChen, Wei-Zenen_US
dc.contributor.authorRen Zhiyuanen_US
dc.date.accessioned2018-08-21T05:56:39Z-
dc.date.available2018-08-21T05:56:39Z-
dc.date.issued2015-01-01en_US
dc.identifier.issn2162-7541en_US
dc.identifier.urihttp://hdl.handle.net/11536/146454-
dc.description.abstractThis paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time Delta Sigma analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 mu W. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm(2).en_US
dc.language.isoen_USen_US
dc.subjectULVen_US
dc.subjectULPen_US
dc.subjectCT-Delta Sigma ADCen_US
dc.titleA 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converteren_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000398709000235en_US
Appears in Collections:Conferences Paper