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dc.contributor.authorLee, Kao-Chien_US
dc.contributor.authorWu, Kai-Chiangen_US
dc.contributor.authorTsai, Chih-Yingen_US
dc.contributor.authorChao, Mango Chia-Tsoen_US
dc.date.accessioned2018-08-21T05:56:46Z-
dc.date.available2018-08-21T05:56:46Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/146629-
dc.description.abstractAs the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.en_US
dc.language.isoen_USen_US
dc.titleFast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparatorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000403393000012en_US
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