Digital Low-Dropout Regulator with Anti PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multicore Processor

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tsou, Wen-Jie	en_US
dc.contributor.author	Yang, Wen-Hau	en_US
dc.contributor.author	Lin, Jian-He	en_US
dc.contributor.author	Chen, Hsin	en_US
dc.contributor.author	Chen, Ke-Horng	en_US
dc.contributor.author	Wey, Chin-Long	en_US
dc.contributor.author	Lin, Ying-Hsi	en_US
dc.contributor.author	Lin, Shian-Ru	en_US
dc.contributor.author	Tsai, Tsung-Yen	en_US
dc.date.accessioned	2018-08-21T05:56:47Z	-
dc.date.available	2018-08-21T05:56:47Z	-
dc.date.issued	2017-01-01	en_US
dc.identifier.issn	0193-6530	en_US
dc.identifier.uri	http://hdl.handle.net/11536/146637	-
dc.language.iso	en_US	en_US
dc.title	Digital Low-Dropout Regulator with Anti PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multicore Processor	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)	en_US
dc.citation.spage	338	en_US
dc.citation.epage	338	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.identifier.wosnumber	WOS:000403393800140	en_US
顯示於類別：	會議論文