完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Jian-Hao | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2018-08-21T05:56:52Z | - |
dc.date.available | 2018-08-21T05:56:52Z | - |
dc.date.issued | 2017-01-01 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146756 | - |
dc.description.abstract | We analyze the variability of 7T hybrid TFET-MOSFET SRAM and 8T MOSFET SRAM in monolithic 3D technology operating at ultra-low voltage. The impacts of work function variation (WFV) and line edge roughness (LER) on SRAM cell stability, leakage power and performance are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and LER have different impacts on read disturb and V-write,V- 0, which dominate SRAM stability and is determined by the distinct current drive of TFET and MOSFET. The performance is influenced by the different variations of gate capacitance (C-g) under WFV and LER. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000408991800022 | en_US |
顯示於類別: | 會議論文 |