完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yu, Chang-Hung | en_US |
dc.contributor.author | Zheng, Jun-Teng | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2018-08-21T05:56:52Z | - |
dc.date.available | 2018-08-21T05:56:52Z | - |
dc.date.issued | 2017-01-01 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146758 | - |
dc.description.abstract | We comprehensively evaluate and benchmark the performance of pass-transistor logic (PTL) circuits using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 node. Our study indicates that the higher V-T of bilayer TMD devices significantly degrades the performance of single pass-transistor based circuits compared with the monolayer counterparts despite the higher mobility of bilayer TMD devices. The effect can be mitigated by using full transmission gate or providing a complementary path. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000408991800024 | en_US |
顯示於類別: | 會議論文 |