完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Yu-Huei | en_US |
dc.contributor.author | Huang, Tzu-Chi | en_US |
dc.contributor.author | Yang, Yao-Yi | en_US |
dc.contributor.author | Chou, Wen-Shen | en_US |
dc.contributor.author | Chen, Ke-Horng | en_US |
dc.contributor.author | Huang, Chen-Chih | en_US |
dc.contributor.author | Lin, Ying-Hsi | en_US |
dc.date.accessioned | 2014-12-08T15:20:39Z | - |
dc.date.available | 2014-12-08T15:20:39Z | - |
dc.date.issued | 2011-11-01 | en_US |
dc.identifier.issn | 0018-9200 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2011.2164019 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/14681 | - |
dc.description.abstract | A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm(2) and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Cross regulation | en_US |
dc.subject | energy bypass mechanism | en_US |
dc.subject | energy delivery path | en_US |
dc.subject | load transient response | en_US |
dc.subject | output voltage ripple | en_US |
dc.subject | power conversion efficiency | en_US |
dc.subject | single-inductor dual-output (SIDO) converter | en_US |
dc.title | Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/JSSC.2011.2164019 | en_US |
dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
dc.citation.volume | 46 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 2488 | en_US |
dc.citation.epage | 2499 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000296234100006 | - |
dc.citation.woscount | 10 | - |
顯示於類別: | 期刊論文 |