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dc.contributor.authorJi, Chengen_US
dc.contributor.authorWu, Chaoen_US
dc.contributor.authorChang, Li-Pinen_US
dc.contributor.authorShi, Liangen_US
dc.contributor.authorXue, Jasonen_US
dc.date.accessioned2018-08-21T05:56:55Z-
dc.date.available2018-08-21T05:56:55Z-
dc.date.issued2016-01-01en_US
dc.identifier.urihttp://dx.doi.org/10.1145/2968478.2968503en_US
dc.identifier.urihttp://hdl.handle.net/11536/146827-
dc.description.abstractNAND flash memory has been the default storage component in mobile systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of mobile storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles: Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Experimental results show that MAP improved upon traditional I/O schedulers by 30% and 8% in terms of read and write latencies, respectively.en_US
dc.language.isoen_USen_US
dc.titleI/O Scheduling with Mapping Cache Awareness for Flash Based Storage Systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2968478.2968503en_US
dc.identifier.journal2016 PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE (EMSOFT)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000414220100021en_US
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