完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Sean Shih-Ying | en_US |
dc.contributor.author | Lee, Chieh-Jui | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.date.accessioned | 2018-08-21T05:56:55Z | - |
dc.date.available | 2018-08-21T05:56:55Z | - |
dc.date.issued | 2012-01-01 | en_US |
dc.identifier.issn | 1530-1591 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146837 | - |
dc.description.abstract | In this paper, an optimization methodology using agglomerative-based clustering for number of flip-flop reduction and signal wirelength minimization is proposed. Comparing to previous works on flip-flop reduction, our method can obtain an optimal tradeoff curve between flip-flop number reduction and increase in signal wirelength. Our proposed methodology outperforms [1] and [12] in both reducing number of flip-flops and minimizing increase in signal wirelength. In comparison with [9], our methodology obtains a tradeoff of 15.8% reduction in flip-flop's signal wirelength with 16.9%additional flip-flops. Due to the nature of agglomerative clustering, when relocating flip-flops, our proposed method minimizes total displacement by an average of 5.9%, 8.0%, 181.4% in comparison with [12], [1] and [9] respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012) | en_US |
dc.citation.spage | 1391 | en_US |
dc.citation.epage | 1396 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000415126300155 | en_US |
顯示於類別: | 會議論文 |