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dc.contributor.authorLiu, Sean Shih-Yingen_US
dc.contributor.authorLee, Chieh-Juien_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2018-08-21T05:56:55Z-
dc.date.available2018-08-21T05:56:55Z-
dc.date.issued2012-01-01en_US
dc.identifier.issn1530-1591en_US
dc.identifier.urihttp://hdl.handle.net/11536/146837-
dc.description.abstractIn this paper, an optimization methodology using agglomerative-based clustering for number of flip-flop reduction and signal wirelength minimization is proposed. Comparing to previous works on flip-flop reduction, our method can obtain an optimal tradeoff curve between flip-flop number reduction and increase in signal wirelength. Our proposed methodology outperforms [1] and [12] in both reducing number of flip-flops and minimizing increase in signal wirelength. In comparison with [9], our methodology obtains a tradeoff of 15.8% reduction in flip-flop's signal wirelength with 16.9%additional flip-flops. Due to the nature of agglomerative clustering, when relocating flip-flops, our proposed method minimizes total displacement by an average of 5.9%, 8.0%, 181.4% in comparison with [12], [1] and [9] respectively.en_US
dc.language.isoen_USen_US
dc.titleAgglomerative-Based Flip-Flop Merging with Signal Wirelength Optimizationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalDESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)en_US
dc.citation.spage1391en_US
dc.citation.epage1396en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000415126300155en_US
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