Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Pan, Po-Cheng | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.contributor.author | Lin, Chien-Chih | en_US |
dc.date.accessioned | 2018-08-21T05:56:55Z | - |
dc.date.available | 2018-08-21T05:56:55Z | - |
dc.date.issued | 2013-01-01 | en_US |
dc.identifier.issn | 1530-1591 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146843 | - |
dc.description.abstract | This paper presents an agile hierarchical synthesis framework for analog circuit. To acknowledge the limitation for a given topology analog circuit, this hierarchical synthesis work proposes a performance exploration technique and a non-uniform-step simulation process. Apart from spec targeted designs, this proposed approach can help to search the solutions better than designers' expectation. A parallel genetic algorithm (PAGE) method is employed for performance exploration. Unlike other evolution-based topology explorations, this is the first method that regards performance constraints as input genome for evolution and resolves the multiple-objective problem with the multiple-population feature. Populations of selected performance are transfered to device variables by re-targeting technique. Based on a normalization of device variable distribution, a probabilistic stochastic simulation significantly reduces the convergence time to find the global optima of circuit performance. Experimental results show that our approach on radio-frequency distributed amplifier (RFDA) and folded cascode operational amplifier (Op-Amp) in different technologies can obtain better runtime and higher quality in analog synthesis. | en_US |
dc.language.iso | en_US | en_US |
dc.title | PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | DESIGN, AUTOMATION & TEST IN EUROPE | en_US |
dc.citation.spage | 1849 | en_US |
dc.citation.epage | 1854 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000415129400354 | en_US |
Appears in Collections: | Conferences Paper |