Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability

標題:	Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
作者:	Su, C. -J. Hong, T. -C. Tsou, Y. -C. Hou, F. -J. Sung, P. -J. Yeh, M. -S. Wan, C. -C. Kao, K. -H. Tang, Y. -T. Chiu, C. -H. Wang, C. -J. Chung, S. -T. You, T. -Y. Huang, Y. -C. Wu, C. -T. Lin, K. -L. Luo, G. -L. Huang, K. -P. Lee, Y. -J. Chao, T. -S. Wu, W. -F. Huang, G. -W. Shieh, J. -M. Yeh, W. -K. Wang, Y. -H. 電子物理學系電子工程學系及電子研究所 Department of Electrophysics Department of Electronics Engineering and Institute of Electronics
公開日期:	1-一月-2017
摘要:	Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. I-ON/I-OFF ratios higher than 10(7) and 10(6) for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.
URI:	http://hdl.handle.net/11536/146908
ISSN:	2380-9248
期刊:	2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
顯示於類別：	會議論文