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dc.contributor.authorChen, Hung-Chengen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2018-08-21T05:57:00Z-
dc.date.available2018-08-21T05:57:00Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/146924-
dc.description.abstractRate distortion optimization helps decide the best coding mode and partition to improve coding efficiency, but suffers from serious data dependency and complexity that hinders an efficient hardware encoder implementation. Thus, this paper presents a hardware-friendly fast rate-distortion method and its design. For rate estimation, we propose a context group adaptive entropy based method for more precise estimation and parallel computation that is applied to both intra and inter predictions instead of intra prediction only as in previous approaches. For distortion estimation, we use the transform domain instead of spatial domain computation to save inverse discrete transform computation and image reconstruction, and reduce cost further by adopting fixed zero sub-blocks in the high frequency part for 32x32 and 16x16 blocks. The simulation results shows 1.77% BD rate loss in average. The proposed hardware design adopts the interleaved Luma/Chroma coding schedule to improve hardware utilization. The final implementation with TSMC 40nm CMOS process can achieve real time 4Kx2K@30fps encoding with 57.95K gate count while operating under 400MHz clock frequency.en_US
dc.language.isoen_USen_US
dc.subjectRDOen_US
dc.subjectHEVCen_US
dc.subjecthardware designen_US
dc.titleFast Rate Distortion Optimization With Adaptive Context Group Modeling For HEVCen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage826en_US
dc.citation.epage829en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000424890100213en_US
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