標題: Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect
作者: Lin, Ming-Huei
Shih, Yi-Jia
Liu, Chien
Chiu, Yu-Chien
Fan, Chia-Chi
Liou, Guan-Lin
Cheng, Chun-Hu
Chang, Chun-Yen
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2017
摘要: This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.
URI: http://hdl.handle.net/11536/146934
ISSN: 2161-4636
期刊: 2017 SILICON NANOELECTRONICS WORKSHOP (SNW)
起始頁: 47
結束頁: 48
Appears in Collections:Conferences Paper