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dc.contributor.authorLee, Chiou-Yngen_US
dc.contributor.authorFan, Chia-Chenen_US
dc.contributor.authorYuan, Shyan-Mingen_US
dc.date.accessioned2018-08-21T05:57:02Z-
dc.date.available2018-08-21T05:57:02Z-
dc.date.issued2017-01-01en_US
dc.identifier.urihttp://dx.doi.org/10.1109/CIAPP.2017.8167267en_US
dc.identifier.urihttp://hdl.handle.net/11536/146960-
dc.description.abstractDigit-serial polynomial basis multipliers over GF(2(m)) are broadly applied in elliptic curve cryptography, because squaring and polynomial reduction in GF(2(m)) are simple operations. In this paper, we define a partial product formula to derive a new digit-serial three-operand multiplication algorithm. On the basis of the proposed algorithm, we have derived a new digit-serial structures for computing three-operand multiplication. Our proposed structures can reduce latency (clock cycles) by approximately 50% compared to the existing digit-serial two-operand multipliers used to perform three-operand multiplication. Therefore, the proposed structure can achieve high-throughput designs. According to the analysis reports, the advantages of the proposed designs are a short critical path, a low area-delay product, and a high throughput.en_US
dc.language.isoen_USen_US
dc.subjectthree-operand multiplicationen_US
dc.subjectdigit-serial multiplieren_US
dc.subjectbinary extension fieldsen_US
dc.titleNew Digit-Serial Three-Operand Multiplier over Binary Extension Fields for High-Performance Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/CIAPP.2017.8167267en_US
dc.identifier.journal2017 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND APPLICATIONS (ICCIA)en_US
dc.citation.spage498en_US
dc.citation.epage502en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000425460800099en_US
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