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dc.contributor.authorHuang, Juinn-Daren_US
dc.contributor.authorChen, Yi-Hangen_US
dc.contributor.authorLu, Jia-Shinen_US
dc.date.accessioned2018-08-21T05:57:11Z-
dc.date.available2018-08-21T05:57:11Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn2324-8432en_US
dc.identifier.urihttp://hdl.handle.net/11536/147153-
dc.description.abstractAs fabrication process exploits even deeper submicron technology, power consumption is becoming one of the most critical obstacles in electronic circuit and system designs nowadays. Meanwhile, the leakage power is dominating the power consumption. Various emerging nanodevices have been developed to tackle the leakage power issue in recent years. The single-electron transistor (SET) is regarded as one of the most promising devices since several works have successfully demonstrated that it can operate with only few electrons at room temperature. Therefore, the reconfigurable SET array has been proposed to continue Moore's Law due to its ultra-low power consumption. Nevertheless, most existing synthesis algorithms assume the given SET array is defect-free. Hence, mapping a correct synthesis outcome onto a faulty SET array still yields an erroneous result. In this paper, we propose a new synthesis algorithm that guarantees the correct functionality in the presence of defects. Furthermore, the proposed technique can sometimes benefit from those defects to further reduce the mapping area. In certain cases, the required area in a faulty SET array is even smaller than that in a fault-free one. Experimental results show that our new algorithm can synthesize moderately large circuits in a reasonable runtime and achieve an area reduction of 14% as compared to the prior art.en_US
dc.language.isoen_USen_US
dc.titleDefect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arraysen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2017 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC)en_US
dc.citation.spage184en_US
dc.citation.epage189en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000427529500035en_US
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