完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Wen-Hao | en_US |
dc.contributor.author | Li, Yih-Lang | en_US |
dc.date.accessioned | 2019-04-02T06:01:01Z | - |
dc.date.available | 2019-04-02T06:01:01Z | - |
dc.date.issued | 2014-04-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2013.2293053 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/147701 | - |
dc.description.abstract | Traditional solutions to antenna effect, such as jumper insertion and diode insertion performed at post-route stage may produce extra vias and degrade circuit performance. Previous work suggests combining layer assignment, jumper insertion, and diode insertion together to achieve a better design quality with less additional cost. Based on our observations on global and local antenna violations, this paper proposes an antenna-safe single-net layer assignment (AS-SLA), which first enumerates all antenna-safe layer assignment solutions of a net, and then extracts the minimum-cost one for the net. AS-SLA can minimize via count and separators as well. In addition, an antenna avoidance layer assignment flow (AALA) adopting AS-SLA as its kernel not only avoids global antenna violations, but also eliminates local antenna violations. Experimental results reveal that, in 16 benchmarks, AALA can yield ten antenna-violation-free assignments, while the algorithms of other works yield no antenna-violation-free assignment. However, AALA performs about seven times slower than other antenna-aware layer assignment algorithm. Accordingly, two acceleration techniques are proposed to reduce the runtime of AALA by 57.6%. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Antenna effect | en_US |
dc.subject | design for manufacturability | en_US |
dc.subject | global routing | en_US |
dc.subject | layer assignment | en_US |
dc.subject | separator | en_US |
dc.title | Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2013.2293053 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 33 | en_US |
dc.citation.spage | 613 | en_US |
dc.citation.epage | 626 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000338135300011 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |