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dc.contributor.authorLin, Jer-Yien_US
dc.contributor.authorTsai, Chan-Yien_US
dc.contributor.authorShen, Chiuan-Hueien_US
dc.contributor.authorChung, Chun-Chihen_US
dc.contributor.authorKumar, Malkundi Puttaveerappa Vijayen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2019-04-02T05:58:35Z-
dc.date.available2019-04-02T05:58:35Z-
dc.date.issued2018-09-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2018.2858227en_US
dc.identifier.urihttp://hdl.handle.net/11536/148066-
dc.description.abstractIn this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n(+) active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a "variable" channel, in which the conduction thickness is thinner or thicker than the physical n(+) thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of I-ON, V-T, S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (I-ON/S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record I-ON , which makes it as a promising device for 3-D integrated nanoelectronics.en_US
dc.language.isoen_USen_US
dc.subjectVariable channel (VC)en_US
dc.subjectnanosheet (NS)en_US
dc.subjectjunctionless (JL)en_US
dc.subjectbody dopingen_US
dc.subjectpolycrystalline siliconen_US
dc.titleVariable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2018.2858227en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume39en_US
dc.citation.spage1326en_US
dc.citation.epage1329en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000443054700014en_US
dc.citation.woscount0en_US
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