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dc.contributor.authorLin, Chien-Hsuehen_US
dc.contributor.authorTsai, Chih-Yingen_US
dc.contributor.authorLee, Kao-Chien_US
dc.contributor.authorYu, Sung-Chuen_US
dc.contributor.authorLiau, Wen-Rongen_US
dc.contributor.authorHou, Alex Chun-Liangen_US
dc.contributor.authorChen, Ying-Yenen_US
dc.contributor.authorKuo, Chun-Yien_US
dc.contributor.authorLee, Jih-Nungen_US
dc.contributor.authorChao, Mango C. T.en_US
dc.date.accessioned2019-04-02T06:00:47Z-
dc.date.available2019-04-02T06:00:47Z-
dc.date.issued2018-10-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2017.2783304en_US
dc.identifier.urihttp://hdl.handle.net/11536/148193-
dc.description.abstractTo measure the variation of device V-t requires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V-t for a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V-t based only on the combined I-d measured from parallel connected DUTs. The proposed framework can further minimize the total number of I-d measurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R -squared for predicting either V-t mean or V-t variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3x speedup on overall test time for test structures with 800 DUTs.en_US
dc.language.isoen_USen_US
dc.subjectMachine learningen_US
dc.subjectmodel-based random forest (MBRF)en_US
dc.subjectthreshold voltageen_US
dc.subjectwafer acceptance test (WAT)en_US
dc.titleA Model-Based-Random-Forest Framework for Predicting V-t Mean and Variance Based on Parallel I-d Measurementen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2017.2783304en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume37en_US
dc.citation.spage2139en_US
dc.citation.epage2151en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000445264200018en_US
dc.citation.woscount0en_US
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