完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Chien-Hsueh | en_US |
dc.contributor.author | Tsai, Chih-Ying | en_US |
dc.contributor.author | Lee, Kao-Chi | en_US |
dc.contributor.author | Yu, Sung-Chu | en_US |
dc.contributor.author | Liau, Wen-Rong | en_US |
dc.contributor.author | Hou, Alex Chun-Liang | en_US |
dc.contributor.author | Chen, Ying-Yen | en_US |
dc.contributor.author | Kuo, Chun-Yi | en_US |
dc.contributor.author | Lee, Jih-Nung | en_US |
dc.contributor.author | Chao, Mango C. T. | en_US |
dc.date.accessioned | 2019-04-02T06:00:47Z | - |
dc.date.available | 2019-04-02T06:00:47Z | - |
dc.date.issued | 2018-10-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2017.2783304 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/148193 | - |
dc.description.abstract | To measure the variation of device V-t requires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V-t for a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V-t based only on the combined I-d measured from parallel connected DUTs. The proposed framework can further minimize the total number of I-d measurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R -squared for predicting either V-t mean or V-t variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3x speedup on overall test time for test structures with 800 DUTs. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Machine learning | en_US |
dc.subject | model-based random forest (MBRF) | en_US |
dc.subject | threshold voltage | en_US |
dc.subject | wafer acceptance test (WAT) | en_US |
dc.title | A Model-Based-Random-Forest Framework for Predicting V-t Mean and Variance Based on Parallel I-d Measurement | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2017.2783304 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 37 | en_US |
dc.citation.spage | 2139 | en_US |
dc.citation.epage | 2151 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000445264200018 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |