完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, CF | en_US |
dc.contributor.author | Tseng, WT | en_US |
dc.contributor.author | Feng, MS | en_US |
dc.date.accessioned | 2019-04-02T05:58:40Z | - |
dc.date.available | 2019-04-02T05:58:40Z | - |
dc.date.issued | 1998-12-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.37.6364 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/148224 | - |
dc.description.abstract | Characteristics of plasma-enhanced chemical vapor deposited (PECVD) SiO2/SiNx passivation layers are modified to improve and optimize electrical performances such as program/erase cycle and hot carrier reliability of floating-gate nonvolatile memory devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics also correspond to increased program/erase cycles and lower % hot-carrier linear drain current (I-dlin) degradation An increase in RI from 1.520 to 1.675 translates to a rise in program/erase cycles from 17.3 K to 32 K and a fall in I-dlin from 8.2% to 4.9%. Further improvement in device performance is fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. Water diffusion from oxide and hydrogen release from nitride are both responsible for hot carrier drain current degradation and loss in program/erase cycles. The utilization of a high-RI oxide in conjunction with a low hydrogen content nitride would give rise to the optimal device reliability. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | non-volatile memories | en_US |
dc.subject | hot carrier | en_US |
dc.subject | device reliability | en_US |
dc.subject | PECVD | en_US |
dc.subject | passivation | en_US |
dc.title | Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performance | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.37.6364 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
dc.citation.volume | 37 | en_US |
dc.citation.spage | 6364 | en_US |
dc.citation.epage | 6368 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000078190000015 | en_US |
dc.citation.woscount | 7 | en_US |
顯示於類別: | 期刊論文 |