Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, Po-Hung | en_US |
dc.contributor.author | Cheng, Hao-Chung | en_US |
dc.contributor.author | Ai, Yi-An | en_US |
dc.contributor.author | Chung, Wang-Ting | en_US |
dc.date.accessioned | 2019-04-02T05:57:57Z | - |
dc.date.available | 2019-04-02T05:57:57Z | - |
dc.date.issued | 2018-12-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2018.2864922 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/148552 | - |
dc.description.abstract | This paper proposes a dual-mode digital buck converter with an automatic mode-select feature in a 0.18-mu m CMOS for self-powered Internet-of-Things applications. The proposed converter combines the digital pulsewidth modulation and the proposed predetermined pulse-frequency modulation (PPFM) techniques to achieve both a high conversion efficiency and a wide output power range. The proposed PPFM technique calculates the appropriate OFF time of the power transistor in advance, eliminating the additional power budget requirement of the conventional zero-crossing detection circuit. From the results, it can be seen that the conversion efficiency improves by 21% under ultralight-load conditions. The available input voltage (V-IN) ranges from 0.55 to 1.8 V for a wide variety of energy harvesters, and the output voltage (V-OUT) ranges from 0.3 to 0.55 V to power the energy-efficient CMOS digital circuits. The proposed dual-mode digital buck converter achieves a maximum conversion efficiency of 90.5%, with an output power ranging from 25 nW to 10 mW. Owing to the proposed PPFM technique, the converter achieves a power conversion efficiency of more than 80%, with an output power of 200 nW to 10 mW. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Automatic mode selection | en_US |
dc.subject | buck converter | en_US |
dc.subject | dual mode | en_US |
dc.subject | energy harvesting | en_US |
dc.title | Automatic Mode-Selected Energy Harvesting Interface With > 80% Power Efficiency Over 200 nW to 10 mW | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2018.2864922 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 26 | en_US |
dc.citation.spage | 2898 | en_US |
dc.citation.epage | 2906 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000451999000031 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Articles |