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dc.contributor.authorLin, Kuen-Weyen_US
dc.contributor.authorLin, Yeh-Shengen_US
dc.contributor.authorLi, Yih-Langen_US
dc.contributor.authorLin, Rung-Binen_US
dc.date.accessioned2019-04-02T06:00:44Z-
dc.date.available2019-04-02T06:00:44Z-
dc.date.issued2018-07-01en_US
dc.identifier.issn1084-4309en_US
dc.identifier.urihttp://dx.doi.org/10.1145/3177878en_US
dc.identifier.urihttp://hdl.handle.net/11536/148726-
dc.description.abstractOwing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches for the multilayer obstacle-avoiding rectilinear Steiner tree (ML-OARST) problem are thus nonmaze routing-based approaches for runtime issues, yet they cannot be directly applied to deal with additional constraints such as variant edge weights on a routing layer. In this article, we propose the maze routing-based methodology with bounded exploration and path-assessed retracing to reduce runtime and routing cost for the constrained ML-OARST construction problem. The exploration of maze routing is bounded to reduce the runtime; the costs of connecting pins are computed to select Steiner points in the retracing phase. To further reduce the routing cost, we develop a Steiner point-based ripping-up and rebuilding scheme for altering tree topology. Experimental results on industrial and randomly generated benchmarks demonstrate that the proposed methodology can provide a solution with good quality in terms of routing cost and has a significant speedup compared to traditional maze routing. A commercial tool is also used to show the effectiveness of the proposed methodology.en_US
dc.language.isoen_USen_US
dc.subjectLayouten_US
dc.subjectphysical designen_US
dc.subjectroutingen_US
dc.subjectSteiner treeen_US
dc.titleA Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Constructionen_US
dc.typeArticleen_US
dc.identifier.doi10.1145/3177878en_US
dc.identifier.journalACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMSen_US
dc.citation.volume23en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000455950300005en_US
dc.citation.woscount0en_US
Appears in Collections:Articles