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dc.contributor.authorVan, Lan-Daen_US
dc.contributor.authorKhoo, I-Hungen_US
dc.contributor.authorChen, Pei-Yuen_US
dc.contributor.authorReddy, Haranatha (Hari) C.en_US
dc.date.accessioned2019-04-02T05:58:11Z-
dc.date.available2019-04-02T05:58:11Z-
dc.date.issued2019-01-01en_US
dc.identifier.issn1531-636Xen_US
dc.identifier.urihttp://dx.doi.org/10.1109/MCAS.2018.2872665en_US
dc.identifier.urihttp://hdl.handle.net/11536/148878-
dc.description.abstractProfessor Fettweis as far back as 1977 published a paper generalizing McClellan transformation to obtain circular symmetry in 2-D and spherical, hyper-spherical symmetries in multidimensional digital filters [1]. This survey paper presents state-of-the-art two-dimensional (2-D) VLSI digital filter architectures possessing various symmetries in the filter magnitude response. Preceding the symmetry structures, a generalized formulation is given that allows the derivation of various new 2-D VLSI filter structures of any order without global broadcast. Following this, two types (namely, Type 1 [20] and Type 3 [21], [25], [26]) of cost-effective 2-D magnitude symmetry filter architectures possessing diagonal, four-fold rotational, quadrantal, and octagonal symmetries with reduced number of multipliers are given. By combining the identities of the Types-1 and 3 symmetry filter structures, multimode 2-D symmetry filters which enable the above four symmetry modes are discussed. The Type-1 and Type-3 multimode filters can result in a 65.3% cost reduction in terms of number of multipliers compared with the sum of the multipliers of the four individual Type-1 symmetry filter structures studied in this paper. Furthermore, Type-3 has shorter critical path than Type-1 multimode filter. The paper is concluded with the presentation of a 2-D filter design example and a corresponding structure.en_US
dc.language.isoen_USen_US
dc.titleSymmetry Incorporated Cost-Effective Architectures for Two-Dimensional Digital Filtersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/MCAS.2018.2872665en_US
dc.identifier.journalIEEE CIRCUITS AND SYSTEMS MAGAZINEen_US
dc.citation.volume19en_US
dc.citation.spage33en_US
dc.citation.epage54en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000458787300005en_US
dc.citation.woscount0en_US
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