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dc.contributor.authorSHIAU, YHen_US
dc.contributor.authorCHUNG, CPen_US
dc.date.accessioned2019-04-02T05:59:14Z-
dc.date.available2019-04-02T05:59:14Z-
dc.date.issued1994-03-01en_US
dc.identifier.issn0253-3839en_US
dc.identifier.urihttp://dx.doi.org/10.1080/02533839.1994.9677580en_US
dc.identifier.urihttp://hdl.handle.net/11536/149116-
dc.description.abstractSuperscalar processing can improve the performance of a single CPU beyond that of traditional RISC machines by exploiting instruction-level parallelism. It is the objective of this study to design a superscalar system which will best exploit a given program's instruction-level parallelism. Three different architectural models, XPCB, XXPB, and X4P2, are used as vehicles in evaluating system performance and the degree of utilization of each individual functional unit. The XPCB model is used as a preliminary model to analyze the loading breakdowns of the various function types. It was found that the performance improvement of the XPCB model relative to a single-instruction stream model is only about 4.3 percent. In addition, the fixed-point operations are in great demand, and dominate the behavior as well as performance of the processor. Two enhanced models, the XXPB and the X4P2, are suggested to improve on the performance of the XPCB model by distributing fixed-point, and even floating-point operation loads among multiple functional units of the same type(s). Simulations show that the XXPB and X4P2 models can improve the performance of the sequential model by 50.8 and 61.6 percent, respectively.en_US
dc.language.isoen_USen_US
dc.subjectSUPERSCALAR PROCESSINGen_US
dc.subjectARCHITECTURAL MODELen_US
dc.subjectPERFORMANCE EVALUATIONen_US
dc.titleBENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTUREen_US
dc.typeArticleen_US
dc.identifier.doi10.1080/02533839.1994.9677580en_US
dc.identifier.journalJOURNAL OF THE CHINESE INSTITUTE OF ENGINEERSen_US
dc.citation.volume17en_US
dc.citation.spage169en_US
dc.citation.epage177en_US
dc.contributor.department資訊科學與工程研究所zh_TW
dc.contributor.departmentInstitute of Computer Science and Engineeringen_US
dc.identifier.wosnumberWOS:A1994NJ60900002en_US
dc.citation.woscount0en_US
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