標題: | A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz |
作者: | Tseng, Wei-Hsin Fan, Chi-Wei Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Background calibration;current-steering;D/A converters;digital random return-to-zero (DRRZ);digital-analog conversion;digital-to-analog converter (DAC);return-to-zero (RZ) |
公開日期: | 1-十二月-2011 |
摘要: | A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 x 750 mu m(2). It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply. |
URI: | http://dx.doi.org/10.1109/JSSC.2011.2164302 http://hdl.handle.net/11536/14920 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2011.2164302 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 46 |
Issue: | 12 |
起始頁: | 2845 |
結束頁: | 2856 |
顯示於類別: | 期刊論文 |